V4 - Reset timing of CDCM61004
The CDCM61004 PLL is quite sensitive to the timing between startup of the reference oscillator (in our case, VM53S) and the moment its VCO is calibrated. In Issues with output incorrect PLL output frequency have been reported by GSI (using the same PLL).
We checked our startup waveforms (see attachment), it looks like there is about 300 us of headroom between the stabilization of reference clock and PLL start up, so the SPEC design is likely not affected (no incorrect PLL freq has ever been observed)
For future releases, consider changing R245 (pulldown for CDCM61004's \RST pin, not mounted) to a 100 nF capacitor, increasing PLL startup lag to ~10 ms.