PandA 0.9.4 Release

Added by Pietro Fezzardi on 08 Jun 2016 at 18:17

The new version 0.9.4 of the PandA framework has been released

Changelog

  • added support to GCC 5 (GCC 4.9 is still the preferred GCC compiler)
  • improved support to complex builtin data types
  • added an initial support to "Extended Asm – Assembler Instructions with C Expression Operands". In particular, the asm instruction could be used to inline VERILOG/VHDL code in a C source description (done by extending the multiple assembler dialects feature in asm templates: https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html)
  • timing for combinational accelerator is now correctly estimated by the backend synthesis scripts (accelerator that takes a single cycle to complete).
  • added option –serialize-memory-accesses to remove any memory access parallelization. It is mainly useful for debugging purposes.
  • added option –distram-threshold to explicitly control the DISTRIBUTED/ASYNCHRONOUS RAMs inferencing.
  • refactored of simulation/evaluation options
  • added support to STRATIX V and STRATIX IV
  • added support to Virtex4
  • added support to C files for cosimulation
  • added support to out of context synthesis on Altera boards
  • now Lattice ECP3 is fully supported. In particular, the byte enabling feature required by some of the memories instantiated by bambu is implemented by exploiting Lattice PMI (Parameterizable Module Inferencing) library.
  • improved and extended the integration of existing IPs written in Verilog/VHDL.
  • added an example showing how asm could be inlined in the C source code: simple_asm
  • added an example, named file_simulate, showing how open, read, write and close could be used to verify a complex design with datasets coming from a file
  • added an example showing how python could be used to verify the correctness of the HLS process: python-bindings
  • added MachSuite ("MachSuite: Benchmarks for Accelerator Design and Customized Architectures." – 2014 IEEE International Symposium on Workload Characterization.) to examples
  • added benchmarks of "A Survey and Evaluation of FPGA High-Level Synthesis Tools" – IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems to examples
  • added two examples showing how external IPs could be integrated in the HLS flow: IP_integration and led_example
  • improved the VGA example for DE1 and ported to Nexys4 Xilinx prototyping board
  • added two examples showing how it is possible to run two arcade games such as pong and breakout on a Nexys 4 prototyping board without using any processor. The two examples smoothly connect a low level controller for the VGA port plus some GPIO controllers with plain C code describing the game behavior.
  • added a tutorial describing how to use bambu in designing a simple example: led_example
  • refactoring of scripts for technology libraries characterization
  • improved regression scripts: now panda regression consists of about 250K tests
  • assertions check now have to be explicitly disabled also in release
  • done port is now registered whenever it is possible
  • added support to the synthesis of function pointers and to the inter-procedural resource sharing of functions (reference paper is: Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi: Inter-procedural resource sharing in High Level Synthesis through function proxies. FPL 2015: 1-8 )
  • added support to speculative SDC code scheduling (controlled through option –speculative-sdc-scheduling | reference paper is: Code Transformations Based on Speculative SDC Scheduling. ICCAD 2015: 71-77 )
  • added two new experimental setups (BAMBU-BALANCED-MP and BAMBU-BALANCED) oriented to trade-off between area and performances; BAMBU_BALANCED-MP is the new default experimental setup
  • added a discrepancy analysis to verify the correctness of the generated code (controlled through option –discrepancy | reference paper is: Pietro Fezzardi, Michele Castellana, Fabrizio Ferrandi: Trace-based automated logical debugging for high-level synthesis generated circuits. ICCD 2015: 251-258 )
  • added common subexpression elimination step
  • reset can now be active high or active low (controlled through option –reset-level)
  • added support to file IO libc functions: open, read, write and close.
  • added support to assert function.
  • added support to libc functions: stpcpy stpncpy strcasecmp strcasestr strcat strchr strchrnul strcmp strcpy strcspn strdup strlen strncasecmp strncat strncmp strncpy strndup strnlen strpbrk strrchr strsep strspn strstr strtok bzero bcopy mempcpy memchr memrchr rawmemchr index rindex
  • improved double precision soft-float library
  • added support to single and double precision complex division operations: __divsc3 __divdc3
  • added preliminary support to irreducible loops
  • changed the PandA hardware description license from GPL to LGPL

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