@regsection Memory map summary
@multitable  @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{carrier} @tab
Carrier type and PCB version
@item @code{0x4} @tab
REG @tab
@code{stat} @tab
Status
@item @code{0x8} @tab
REG @tab
@code{ctrl} @tab
Control
@item @code{0xc} @tab
REG @tab
@code{rst} @tab
Reset Register
@end multitable 
@regsection @code{carrier} - Carrier type and PCB version
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab R/O @tab
@code{PCB_REV}
@tab @code{X} @tab 
PCB revision
@item @code{15...5}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab 
Reserved register
@item @code{31...16}
@tab R/O @tab
@code{TYPE}
@tab @code{X} @tab 
Carrier type
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{pcb_rev} @tab Binary coded PCB layout revision.
@item @code{reserved} @tab Ignore on read, write with 0's.
@item @code{type} @tab Carrier type identifier@*1 = SPEC@*2 = SVEC@*3 = VFC@*4 = SPEXI
@end multitable
@regsection @code{stat} - Status
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{FMC0_PRES}
@tab @code{X} @tab 
FMC 1 presence
@item @code{1}
@tab R/O @tab
@code{FMC1_PRES}
@tab @code{X} @tab 
FMC 2 presence
@item @code{2}
@tab R/O @tab
@code{SYS_PLL_LCK}
@tab @code{X} @tab 
System clock PLL status
@item @code{3}
@tab R/O @tab
@code{DDR0_CAL_DONE}
@tab @code{X} @tab 
DDR3 bank 4 calibration status
@item @code{4}
@tab R/O @tab
@code{DDR1_CAL_DONE}
@tab @code{X} @tab 
DDR3 bank 5 calibration status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_pres} @tab 0: FMC slot 1 is populated@*1: FMC slot 1 is not populated.
@item @code{fmc1_pres} @tab 0: FMC slot 2 is populated@*1: FMC slot 2 is not populated.
@item @code{sys_pll_lck} @tab 0: not locked@*1: locked.
@item @code{ddr0_cal_done} @tab 0: not done@*1: done.
@item @code{ddr1_cal_done} @tab 0: not done@*1: done.
@end multitable
@regsection @code{ctrl} - Control
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{15...0}
@tab R/W @tab
@code{FP_LEDS_MAN}
@tab @code{0} @tab 
Front panel LED manual control
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fp_leds_man} @tab Height front panel LED, two bits per LED.@*00 = OFF@*01 = Green@*10 = Red@*11 = Orange
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{FMC0_N}
@tab @code{X} @tab 
State of the FMC 1 reset line
@item @code{1}
@tab R/W @tab
@code{FMC1_N}
@tab @code{X} @tab 
State of the FMC 2 reset line
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
@item @code{fmc1_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
@end multitable
