sim_tool = "modelsim"
top_module="main"
syn_device="xc6slx45t"
sim_top="main"

action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"

include_dirs = [
    "../include",
    "../../sim",
    fetchto + "/gn4124-core/hdl/gn4124core/sim/gn4124_bfm",
    fetchto + "/general-cores/sim",
    fetchto + "/general-cores/modules/wishbone/wb_lm32/src",
    #fetchto + "/ddr3-sp6-core/hdl/sim/",
    fetchto + "/wr-cores/sim",
]

vcom_opt = "-mixedsvvh l"
files = [ "main.sv" ]


modules = { "local" :  [ "../../top/spec", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ] }

ctrls = ["bank3_32b_32b"]