..
  SPDX-License-Identifier: CC-BY-SA-4.0+
  SPDX-FileCopyrightText: 2022 CERN

=====================
SVEC FMC-TDC-1NS-5CHA
=====================

The memory map is divided in two parts:
the :ref:`Carrier (SVEC) <SVEC base regs>` part common to
all SVEC designs, and two memory regions for TDCs
(:ref:`TDC1 <TDC1 base regs>` and :ref:`TDC2 <TDC2 base regs>`) part specific to the
FMC-TDC-1NS-5CHA mezzanine.

.. only:: latex

   .. include:: regs/svec_ref_fmc_tdc_mmap.rst

.. raw:: html
   :file: regs/svec_ref_fmc_tdc_mmap.htm

.. _`SVEC base regs`:

SVEC base registers
===================

.. only:: latex

   .. include:: regs/svec_base_regs.rst

.. raw:: html
   :file: regs/svec_base_regs.htm


.. _`TDC1 base regs`:

First FMC-TDC-1NS-5CHA
======================

See :ref:`tdc_memory_map`.

.. _`TDC2 base regs`:

Second FMC-TDC-1NS-5CHA
=======================

See :ref:`tdc_memory_map`.
