tdc_onewire_wb

TDC Onewire Master

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Status Register
3.2. Board Temperature
3.3. Board Unique ID (MSW)
3.4. Board Unique ID (LSW)

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Status Register tdc_ow_csr CSR
0x1 REG Board Temperature tdc_ow_temp TEMP
0x2 REG Board Unique ID (MSW) tdc_ow_id_h ID_H
0x3 REG Board Unique ID (LSW) tdc_ow_id_l ID_L

2. HDL symbol

wb_adr_i[1:0] Status Register:
wb_dat_i[31:0] tdc_ow_csr_valid_o
wb_dat_o[31:0] tdc_ow_csr_valid_i
wb_cyc_i tdc_ow_csr_valid_load_o
wb_sel_i[3:0]  
wb_stb_i Board Temperature:
wb_we_i tdc_ow_temp_i[15:0]
wb_ack_o  
wb_err_o Board Unique ID (MSW):
wb_rty_o tdc_ow_id_h_i[31:0]
wb_stall_o  
Board Unique ID (LSW):
tdc_ow_id_l_i[31:0]

3. Register description

3.1. Status Register

HW prefix: tdc_ow_csr
HW address: 0x0
C prefix: CSR
C offset: 0x0
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - VALID

3.2. Board Temperature

HW prefix: tdc_ow_temp
HW address: 0x1
C prefix: TEMP
C offset: 0x4
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TEMP[15:8]
7 6 5 4 3 2 1 0
TEMP[7:0]

3.3. Board Unique ID (MSW)

HW prefix: tdc_ow_id_h
HW address: 0x2
C prefix: ID_H
C offset: 0x8
31 30 29 28 27 26 25 24
ID_H[31:24]
23 22 21 20 19 18 17 16
ID_H[23:16]
15 14 13 12 11 10 9 8
ID_H[15:8]
7 6 5 4 3 2 1 0
ID_H[7:0]

3.4. Board Unique ID (LSW)

HW prefix: tdc_ow_id_l
HW address: 0x3
C prefix: ID_L
C offset: 0xc
31 30 29 28 27 26 25 24
ID_L[31:24]
23 22 21 20 19 18 17 16
ID_L[23:16]
15 14 13 12 11 10 9 8
ID_L[15:8]
7 6 5 4 3 2 1 0
ID_L[7:0]