tdc_eic
TDC EIC
FMC TDC embedded interrrupt controller.
Contents:
1. Memory map summary
2. HDL symbol
3. Register description
3.1. Interrupt disable register
3.2. Interrupt enable register
3.3. Interrupt mask register
3.4. Interrupt status register
5. Interrupts
5.1. FMC TDC timestamps interrupt (FIFO1)
5.2. FMC TDC timestamps interrupt (FIFO2)
5.3. FMC TDC timestamps interrupt (FIFO3)
5.4. FMC TDC timestamps interrupt (FIFO4)
5.5. FMC TDC timestamps interrupt (FIFO5)
5.6. FMC TDC timestamps interrupt (DMA1)
5.7. FMC TDC timestamps interrupt (DMA2)
5.8. FMC TDC timestamps interrupt (DMA3)
5.9. FMC TDC timestamps interrupt (DMA4)
5.10. FMC TDC timestamps interrupt (DMA5)
⇒
|
wb_adr_i[3:0]
|
|
FMC TDC timestamps interrupt (FIFO1):
|
|
⇒
|
wb_dat_i[31:0]
|
|
irq_tdc_fifo1_i
|
←
|
⇐
|
wb_dat_o[31:0]
|
|
|
|
→
|
wb_cyc_i
|
|
FMC TDC timestamps interrupt (FIFO2):
|
|
⇒
|
wb_sel_i[3:0]
|
|
irq_tdc_fifo2_i
|
←
|
→
|
wb_stb_i
|
|
|
|
→
|
wb_we_i
|
|
FMC TDC timestamps interrupt (FIFO3):
|
|
←
|
wb_ack_o
|
|
irq_tdc_fifo3_i
|
←
|
←
|
wb_err_o
|
|
|
|
←
|
wb_rty_o
|
|
FMC TDC timestamps interrupt (FIFO4):
|
|
←
|
wb_stall_o
|
|
irq_tdc_fifo4_i
|
←
|
←
|
wb_int_o
|
|
|
|
|
|
|
FMC TDC timestamps interrupt (FIFO5):
|
|
|
|
|
irq_tdc_fifo5_i
|
←
|
|
|
|
|
|
|
|
|
FMC TDC timestamps interrupt (DMA1):
|
|
|
|
|
irq_tdc_dma1_i
|
←
|
|
|
|
|
|
|
|
|
FMC TDC timestamps interrupt (DMA2):
|
|
|
|
|
irq_tdc_dma2_i
|
←
|
|
|
|
|
|
|
|
|
FMC TDC timestamps interrupt (DMA3):
|
|
|
|
|
irq_tdc_dma3_i
|
←
|
|
|
|
|
|
|
|
|
FMC TDC timestamps interrupt (DMA4):
|
|
|
|
|
irq_tdc_dma4_i
|
←
|
|
|
|
|
|
|
|
|
FMC TDC timestamps interrupt (DMA5):
|
|
|
|
|
irq_tdc_dma5_i
|
←
|
HW prefix:
|
tdc_eic_eic_idr
|
HW address:
|
0x8
|
C prefix:
|
EIC_IDR
|
C offset:
|
0x20
|
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
TDC_DMA5
|
TDC_DMA4
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TDC_DMA3
|
TDC_DMA2
|
TDC_DMA1
|
TDC_FIFO5
|
TDC_FIFO4
|
TDC_FIFO3
|
TDC_FIFO2
|
TDC_FIFO1
|
-
TDC_FIFO1
[write-only]: FMC TDC timestamps interrupt (FIFO1)
write 1: disable interrupt 'FMC TDC timestamps interrupt (FIFO1)'
write 0: no effect
-
TDC_FIFO2
[write-only]: FMC TDC timestamps interrupt (FIFO2)
write 1: disable interrupt 'FMC TDC timestamps interrupt (FIFO2)'
write 0: no effect
-
TDC_FIFO3
[write-only]: FMC TDC timestamps interrupt (FIFO3)
write 1: disable interrupt 'FMC TDC timestamps interrupt (FIFO3)'
write 0: no effect
-
TDC_FIFO4
[write-only]: FMC TDC timestamps interrupt (FIFO4)
write 1: disable interrupt 'FMC TDC timestamps interrupt (FIFO4)'
write 0: no effect
-
TDC_FIFO5
[write-only]: FMC TDC timestamps interrupt (FIFO5)
write 1: disable interrupt 'FMC TDC timestamps interrupt (FIFO5)'
write 0: no effect
-
TDC_DMA1
[write-only]: FMC TDC timestamps interrupt (DMA1)
write 1: disable interrupt 'FMC TDC timestamps interrupt (DMA1)'
write 0: no effect
-
TDC_DMA2
[write-only]: FMC TDC timestamps interrupt (DMA2)
write 1: disable interrupt 'FMC TDC timestamps interrupt (DMA2)'
write 0: no effect
-
TDC_DMA3
[write-only]: FMC TDC timestamps interrupt (DMA3)
write 1: disable interrupt 'FMC TDC timestamps interrupt (DMA3)'
write 0: no effect
-
TDC_DMA4
[write-only]: FMC TDC timestamps interrupt (DMA4)
write 1: disable interrupt 'FMC TDC timestamps interrupt (DMA4)'
write 0: no effect
-
TDC_DMA5
[write-only]: FMC TDC timestamps interrupt (DMA5)
write 1: disable interrupt 'FMC TDC timestamps interrupt (DMA5)'
write 0: no effect
HW prefix:
|
tdc_eic_eic_ier
|
HW address:
|
0x9
|
C prefix:
|
EIC_IER
|
C offset:
|
0x24
|
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
TDC_DMA5
|
TDC_DMA4
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TDC_DMA3
|
TDC_DMA2
|
TDC_DMA1
|
TDC_FIFO5
|
TDC_FIFO4
|
TDC_FIFO3
|
TDC_FIFO2
|
TDC_FIFO1
|
-
TDC_FIFO1
[write-only]: FMC TDC timestamps interrupt (FIFO1)
write 1: enable interrupt 'FMC TDC timestamps interrupt (FIFO1)'
write 0: no effect
-
TDC_FIFO2
[write-only]: FMC TDC timestamps interrupt (FIFO2)
write 1: enable interrupt 'FMC TDC timestamps interrupt (FIFO2)'
write 0: no effect
-
TDC_FIFO3
[write-only]: FMC TDC timestamps interrupt (FIFO3)
write 1: enable interrupt 'FMC TDC timestamps interrupt (FIFO3)'
write 0: no effect
-
TDC_FIFO4
[write-only]: FMC TDC timestamps interrupt (FIFO4)
write 1: enable interrupt 'FMC TDC timestamps interrupt (FIFO4)'
write 0: no effect
-
TDC_FIFO5
[write-only]: FMC TDC timestamps interrupt (FIFO5)
write 1: enable interrupt 'FMC TDC timestamps interrupt (FIFO5)'
write 0: no effect
-
TDC_DMA1
[write-only]: FMC TDC timestamps interrupt (DMA1)
write 1: enable interrupt 'FMC TDC timestamps interrupt (DMA1)'
write 0: no effect
-
TDC_DMA2
[write-only]: FMC TDC timestamps interrupt (DMA2)
write 1: enable interrupt 'FMC TDC timestamps interrupt (DMA2)'
write 0: no effect
-
TDC_DMA3
[write-only]: FMC TDC timestamps interrupt (DMA3)
write 1: enable interrupt 'FMC TDC timestamps interrupt (DMA3)'
write 0: no effect
-
TDC_DMA4
[write-only]: FMC TDC timestamps interrupt (DMA4)
write 1: enable interrupt 'FMC TDC timestamps interrupt (DMA4)'
write 0: no effect
-
TDC_DMA5
[write-only]: FMC TDC timestamps interrupt (DMA5)
write 1: enable interrupt 'FMC TDC timestamps interrupt (DMA5)'
write 0: no effect
HW prefix:
|
tdc_eic_eic_imr
|
HW address:
|
0xa
|
C prefix:
|
EIC_IMR
|
C offset:
|
0x28
|
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
TDC_DMA5
|
TDC_DMA4
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TDC_DMA3
|
TDC_DMA2
|
TDC_DMA1
|
TDC_FIFO5
|
TDC_FIFO4
|
TDC_FIFO3
|
TDC_FIFO2
|
TDC_FIFO1
|
-
TDC_FIFO1
[read-only]: FMC TDC timestamps interrupt (FIFO1)
read 1: interrupt 'FMC TDC timestamps interrupt (FIFO1)' is enabled
read 0: interrupt 'FMC TDC timestamps interrupt (FIFO1)' is disabled
-
TDC_FIFO2
[read-only]: FMC TDC timestamps interrupt (FIFO2)
read 1: interrupt 'FMC TDC timestamps interrupt (FIFO2)' is enabled
read 0: interrupt 'FMC TDC timestamps interrupt (FIFO2)' is disabled
-
TDC_FIFO3
[read-only]: FMC TDC timestamps interrupt (FIFO3)
read 1: interrupt 'FMC TDC timestamps interrupt (FIFO3)' is enabled
read 0: interrupt 'FMC TDC timestamps interrupt (FIFO3)' is disabled
-
TDC_FIFO4
[read-only]: FMC TDC timestamps interrupt (FIFO4)
read 1: interrupt 'FMC TDC timestamps interrupt (FIFO4)' is enabled
read 0: interrupt 'FMC TDC timestamps interrupt (FIFO4)' is disabled
-
TDC_FIFO5
[read-only]: FMC TDC timestamps interrupt (FIFO5)
read 1: interrupt 'FMC TDC timestamps interrupt (FIFO5)' is enabled
read 0: interrupt 'FMC TDC timestamps interrupt (FIFO5)' is disabled
-
TDC_DMA1
[read-only]: FMC TDC timestamps interrupt (DMA1)
read 1: interrupt 'FMC TDC timestamps interrupt (DMA1)' is enabled
read 0: interrupt 'FMC TDC timestamps interrupt (DMA1)' is disabled
-
TDC_DMA2
[read-only]: FMC TDC timestamps interrupt (DMA2)
read 1: interrupt 'FMC TDC timestamps interrupt (DMA2)' is enabled
read 0: interrupt 'FMC TDC timestamps interrupt (DMA2)' is disabled
-
TDC_DMA3
[read-only]: FMC TDC timestamps interrupt (DMA3)
read 1: interrupt 'FMC TDC timestamps interrupt (DMA3)' is enabled
read 0: interrupt 'FMC TDC timestamps interrupt (DMA3)' is disabled
-
TDC_DMA4
[read-only]: FMC TDC timestamps interrupt (DMA4)
read 1: interrupt 'FMC TDC timestamps interrupt (DMA4)' is enabled
read 0: interrupt 'FMC TDC timestamps interrupt (DMA4)' is disabled
-
TDC_DMA5
[read-only]: FMC TDC timestamps interrupt (DMA5)
read 1: interrupt 'FMC TDC timestamps interrupt (DMA5)' is enabled
read 0: interrupt 'FMC TDC timestamps interrupt (DMA5)' is disabled
HW prefix:
|
tdc_eic_eic_isr
|
HW address:
|
0xb
|
C prefix:
|
EIC_ISR
|
C offset:
|
0x2c
|
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
TDC_DMA5
|
TDC_DMA4
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TDC_DMA3
|
TDC_DMA2
|
TDC_DMA1
|
TDC_FIFO5
|
TDC_FIFO4
|
TDC_FIFO3
|
TDC_FIFO2
|
TDC_FIFO1
|
-
TDC_FIFO1
[read/write]: FMC TDC timestamps interrupt (FIFO1)
read 1: interrupt 'FMC TDC timestamps interrupt (FIFO1)' is pending
read 0: interrupt not pending
write 1: clear interrupt 'FMC TDC timestamps interrupt (FIFO1)'
write 0: no effect
-
TDC_FIFO2
[read/write]: FMC TDC timestamps interrupt (FIFO2)
read 1: interrupt 'FMC TDC timestamps interrupt (FIFO2)' is pending
read 0: interrupt not pending
write 1: clear interrupt 'FMC TDC timestamps interrupt (FIFO2)'
write 0: no effect
-
TDC_FIFO3
[read/write]: FMC TDC timestamps interrupt (FIFO3)
read 1: interrupt 'FMC TDC timestamps interrupt (FIFO3)' is pending
read 0: interrupt not pending
write 1: clear interrupt 'FMC TDC timestamps interrupt (FIFO3)'
write 0: no effect
-
TDC_FIFO4
[read/write]: FMC TDC timestamps interrupt (FIFO4)
read 1: interrupt 'FMC TDC timestamps interrupt (FIFO4)' is pending
read 0: interrupt not pending
write 1: clear interrupt 'FMC TDC timestamps interrupt (FIFO4)'
write 0: no effect
-
TDC_FIFO5
[read/write]: FMC TDC timestamps interrupt (FIFO5)
read 1: interrupt 'FMC TDC timestamps interrupt (FIFO5)' is pending
read 0: interrupt not pending
write 1: clear interrupt 'FMC TDC timestamps interrupt (FIFO5)'
write 0: no effect
-
TDC_DMA1
[read/write]: FMC TDC timestamps interrupt (DMA1)
read 1: interrupt 'FMC TDC timestamps interrupt (DMA1)' is pending
read 0: interrupt not pending
write 1: clear interrupt 'FMC TDC timestamps interrupt (DMA1)'
write 0: no effect
-
TDC_DMA2
[read/write]: FMC TDC timestamps interrupt (DMA2)
read 1: interrupt 'FMC TDC timestamps interrupt (DMA2)' is pending
read 0: interrupt not pending
write 1: clear interrupt 'FMC TDC timestamps interrupt (DMA2)'
write 0: no effect
-
TDC_DMA3
[read/write]: FMC TDC timestamps interrupt (DMA3)
read 1: interrupt 'FMC TDC timestamps interrupt (DMA3)' is pending
read 0: interrupt not pending
write 1: clear interrupt 'FMC TDC timestamps interrupt (DMA3)'
write 0: no effect
-
TDC_DMA4
[read/write]: FMC TDC timestamps interrupt (DMA4)
read 1: interrupt 'FMC TDC timestamps interrupt (DMA4)' is pending
read 0: interrupt not pending
write 1: clear interrupt 'FMC TDC timestamps interrupt (DMA4)'
write 0: no effect
-
TDC_DMA5
[read/write]: FMC TDC timestamps interrupt (DMA5)
read 1: interrupt 'FMC TDC timestamps interrupt (DMA5)' is pending
read 0: interrupt not pending
write 1: clear interrupt 'FMC TDC timestamps interrupt (DMA5)'
write 0: no effect
HW prefix:
|
tdc_eic_tdc_fifo1
|
C prefix:
|
TDC_FIFO1
|
Trigger:
|
high level
|
FMC TDC FIFO1 not empty.
HW prefix:
|
tdc_eic_tdc_fifo2
|
C prefix:
|
TDC_FIFO2
|
Trigger:
|
high level
|
FMC TDC FIFO1 not empty.
HW prefix:
|
tdc_eic_tdc_fifo3
|
C prefix:
|
TDC_FIFO3
|
Trigger:
|
high level
|
FMC TDC FIFO3 not empty.
HW prefix:
|
tdc_eic_tdc_fifo4
|
C prefix:
|
TDC_FIFO4
|
Trigger:
|
high level
|
FMC TDC FIFO4 not empty.
HW prefix:
|
tdc_eic_tdc_fifo5
|
C prefix:
|
TDC_FIFO5
|
Trigger:
|
high level
|
FMC TDC FIFO5 not empty.
HW prefix:
|
tdc_eic_tdc_dma1
|
C prefix:
|
TDC_DMA1
|
Trigger:
|
high level
|
FMC TDC DMA1 acquisition ready.
HW prefix:
|
tdc_eic_tdc_dma2
|
C prefix:
|
TDC_DMA2
|
Trigger:
|
high level
|
FMC TDC DMA1 acquisition ready.
HW prefix:
|
tdc_eic_tdc_dma3
|
C prefix:
|
TDC_DMA3
|
Trigger:
|
high level
|
FMC TDC DMA3 acquisition ready.
HW prefix:
|
tdc_eic_tdc_dma4
|
C prefix:
|
TDC_DMA4
|
Trigger:
|
high level
|
FMC TDC DMA4 acquisition ready.
HW prefix:
|
tdc_eic_tdc_dma5
|
C prefix:
|
TDC_DMA5
|
Trigger:
|
high level
|
FMC TDC DMA5 acquisition ready.