System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
Path C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\12.3\ISE_DS\common\bin\nt64;
C:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\		 C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\12.3\ISE_DS\common\bin\nt64;
C:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\		 C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\12.3\ISE_DS\common\bin\nt64;
C:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\		 C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\12.3\ISE_DS\common\bin\nt64;
C:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\
XILINX C:\Xilinx\12.3\ISE_DS\ISE\ C:\Xilinx\12.3\ISE_DS\ISE\ C:\Xilinx\12.3\ISE_DS\ISE\ C:\Xilinx\12.3\ISE_DS\ISE\
XILINX_DSP C:\Xilinx\12.3\ISE_DS\ISE C:\Xilinx\12.3\ISE_DS\ISE C:\Xilinx\12.3\ISE_DS\ISE C:\Xilinx\12.3\ISE_DS\ISE
XILINX_EDK C:\Xilinx\12.3\ISE_DS\EDK C:\Xilinx\12.3\ISE_DS\EDK C:\Xilinx\12.3\ISE_DS\EDK C:\Xilinx\12.3\ISE_DS\EDK
XILINX_PLANAHEAD C:\Xilinx\12.3\ISE_DS\PlanAhead C:\Xilinx\12.3\ISE_DS\PlanAhead C:\Xilinx\12.3\ISE_DS\PlanAhead C:\Xilinx\12.3\ISE_DS\PlanAhead
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   SFpga.prj  
-ifmt   mixed Mixed
-ofn   SFpga  
-ofmt   NGC NGC
-p   xc6slx150t-3-fgg676  
-top   SFpga  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-keep_hierarchy Keep Hierarchy No No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis NO No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets   Auto Auto
-fsm_extract   YES Yes
-fsm_encoding   Auto Auto
-safe_implementation   No No
-fsm_style   LUT LUT
-ram_extract   Yes Yes
-ram_style   Auto Auto
-rom_extract   Yes Yes
-shreg_extract   YES Yes
-rom_style   Auto Auto
-auto_bram_packing   NO No
-resource_sharing   YES Yes
-async_to_sync   NO No
-use_dsp48   Auto Auto
-iobuf   YES Yes
-max_fanout   100000 100000
-bufg   16 16
-register_duplication   YES Yes
-register_balancing   No No
-optimize_primitives   NO No
-use_clock_enable   Auto Auto
-use_sync_set   Auto Auto
-use_sync_reset   Auto Auto
-iob   Auto Auto
-equivalent_register_removal   YES Yes
-slice_utilization_ratio_maxmargin   5 0
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc6slx150t-fgg676-3 None
-uc   SFpga.ucf None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ol Place & Route Effort Level (Overall) high high
-xt Extra Cost Tables 0 0
-ir Use RLOC Constraints OFF OFF
-t Starting Placer Cost Table (1-100) Map 1 0
-intstyle   ise None
-lc LUT Combining off off
-o   SFpga_map.ncd None
-w   true false
-pr Pack I/O Registers/Latches into IOBs off off
-p   xc6slx150t-fgg676-3 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise  
-mt Enable Multi-Threading off off
-ol Place & Route Effort Level (Overall) high std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz
Host PCBE13225 PCBE13225 PCBE13225 PCBE13225
OS Name Microsoft Microsoft Microsoft Microsoft
OS Release major release (build 7600) major release (build 7600) major release (build 7600) major release (build 7600)