target = "xilinx"
action = "synthesis"

modules = {"local" : ["../../../top/spec/demo_yarr/",
                      "../../../modules/rx-core/",
                      "../../../modules/tx-core/",
                      "../../../modules/common/",
                      "../../../modules/coregen/"],
            "git" :   [ "git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
                        "git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::develop",
                        "git://ohwr.org/hdl-core-lib/gn4124-core.git::develop" ]}



syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "yarr"
syn_tool = "ise"
syn_project = "yarr_spec.xise"

fetchto = "../../../ip_cores"

ctrls = ["bank3_32b_32b"]

