-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 6.0 (Build Build 202 06/20/2006)
-- Created on Wed May 02 11:27:03 2007

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY indicators IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		reset : IN STD_LOGIC;
		clk : IN STD_LOGIC;
		clk_en : IN STD_LOGIC;
		STAT_REGS_IN : IN STD_LOGIC_VECTOR(7 downto 0);
		sck : OUT STD_LOGIC;
		sdat : OUT STD_LOGIC;
		strobe : OUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END indicators;


--  Architecture Body

ARCHITECTURE indicators_architecture OF indicators IS

signal LED_data : STD_LOGIC_VECTOR(7 downto 0);


  component hct4094
    generic (
      data_len    : integer;
      glitch_capt : integer);
    port (
      clk     : IN  STD_LOGIC;
      clk_en  : IN  STD_LOGIC;
      reset   : IN  STD_LOGIC;
      data_in : IN  STD_LOGIC_VECTOR(data_len-1 downto 0);
      test1   : OUT STD_LOGIC;
      test2   : OUT STD_LOGIC;
      test3   : OUT STD_LOGIC;
      test4   : OUT STD_LOGIC;
      str     : OUT STD_LOGIC;
      data    : OUT STD_LOGIC;
      sck     : OUT STD_LOGIC);
  end component;
	
BEGIN


	LED_data(7 downto 0) <= STAT_REGS_IN;



  hct4094_1: hct4094
    generic map (
      data_len    => 8,
      glitch_capt => 8)
    port map (
      clk     => clk,
      clk_en  => clk_en,
--      clk_en  => '1',
      reset   => reset,
      data_in => LED_data,
      test1   => open,
      test2   => open,
      test3   => open,
      test4   => open,
      str     => strobe,
      data    => sdat,
      sck     => sck);


  

END indicators_architecture;
