-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.


-- Generated by Quartus II Version 4.1 (Build Build 181 06/29/2004)
-- Created on Wed Sep 22 10:39:11 2004


LIBRARY IEEE ;
LIBRARY lpm ;
USE     IEEE.std_logic_1164.all ;
USE     IEEE.numeric_std.all;
USE     lpm.lpm_components.ALL;
use ieee.std_logic_unsigned.all;
use work.types.all;

--  Entity Declaration

ENTITY REGISTERS IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		CLK : IN STD_LOGIC;
		reset : IN STD_LOGIC;
		status : IN STD_LOGIC_VECTOR(7 downto 0);
		PCI_BEn : IN STD_LOGIC_VECTOR(1 downto 0);
		PCI_FRAMEn : IN STD_LOGIC;
		PCI_IRDYn : IN STD_LOGIC;
		PCI_CLK : IN STD_LOGIC;
		PCI_RESET : IN STD_LOGIC;
		DPRAM_D : IN STD_LOGIC_VECTOR(31 downto 0);
		measurement_done : IN STD_LOGIC;
		armed : IN STD_LOGIC;
		sample : IN STD_LOGIC;
		EXT_out : OUT STD_LOGIC_VECTOR(15 downto 1);
		STAT_LED : OUT STD_LOGIC_VECTOR(7 downto 0);
		PCI_TRDYn : OUT STD_LOGIC;
		PCI_INTn : OUT STD_LOGIC;
		pci_test : OUT STD_LOGIC_VECTOR(7 downto 0);
		sampling_freq : OUT STD_LOGIC_VECTOR(15 downto 0);
		ARM : OUT STD_LOGIC;
		software_trigger : OUT STD_LOGIC;
		sampling_clk_source : OUT STD_LOGIC;
		trig_select : OUT STD_LOGIC;
		Single_Channel_Mode_Channel_number : OUT STD_LOGIC_VECTOR(5 downto 0);
		Single_Channel_Mode : OUT STD_LOGIC;
		DPRAM_A : OUT STD_LOGIC_VECTOR(11 downto 0);
		num_of_measurements : OUT STD_LOGIC_VECTOR(15 downto 0);
		PCI_AD : INOUT STD_LOGIC_VECTOR(15 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END REGISTERS;




--  Architecture Body

ARCHITECTURE REGISTERS_architecture OF REGISTERS IS
----------------------
-- Signal Declaration
----------------------


-- Internal Registers

signal VME_R_registers : SHAREDREGISTERS(15 downto 0);  -- this is an array of VLong
signal VME_RW_registers : SHAREDREGISTERS(15 downto 0);  -- this is an array of VLong

signal INT_IN  : std_logic;      --interrupt reguest to PCI slave
signal relays  : std_logic_vector(7 downto 0);                              

signal write_result0_dpram,write_result1_dpram, write_result_synchr, write_offset_synchr  : std_logic;

--DPRAm access signals from PCI slave
signal  REGS_RW_DAT_READ    :    	STD_LOGIC_VECTOR(31 downto 0);
signal  REGS_RW_DAT_WRITE   :   	STD_LOGIC_VECTOR(31 downto 0);
signal  REGS_RW_ADDR        : 		STD_LOGIC_VECTOR(4 downto 0);
signal  REGS_RW_WREN        :     	STD_LOGIC;
signal  REGS_R_DAT_READ     :     	STD_LOGIC_VECTOR(31 downto 0);
signal  REGS_R_ADDR         :     	STD_LOGIC_VECTOR(4 downto 0);

signal  DPRAM0_RW_DAT_READ  :     	STD_LOGIC_VECTOR(31 downto 0);
signal  DPRAM0_RW_DAT_WRITE :     	STD_LOGIC_VECTOR(31 downto 0);
signal  DPRAM0_RW_ADDR      :     	STD_LOGIC_VECTOR(6 downto 0);
signal  DPRAM0_RW_WREN      :     	STD_LOGIC;
signal  DPRAM1_R_DAT_READ   :     	STD_LOGIC_VECTOR(31 downto 0);
signal  DPRAM1_R_ADDR       :     	STD_LOGIC_VECTOR(6 downto 0);
signal  DPRAM2_R_DATA       :     	STD_LOGIC_VECTOR(31 downto 0);
signal  DPRAM2_R_ADDR       :     	STD_LOGIC_VECTOR(10 downto 0);
signal  DPRAM3_R_DATA       :     	STD_LOGIC_VECTOR(31 downto 0);
signal  DPRAM3_R_ADDR       :     	STD_LOGIC_VECTOR(10 downto 0);




--DPRAM access signals from integrator state machine
signal 	PARAM_DPRAM0_RD_ADDRESS	:     STD_LOGIC_VECTOR(6 downto 0);
signal	PARAM_DPRAM0_RD_DATA	:     STD_LOGIC_VECTOR(31 downto 0);
signal	RESULT_DPRAM1_W_ADDRESS	:     STD_LOGIC_VECTOR(6 downto 0);
signal	RESULT_DPRAM1_W_DATA	:     STD_LOGIC_VECTOR(31 downto 0);
signal	RESULT_DPRAM1_W_WREN	:     STD_LOGIC;
signal  synchr_result1,synchr_result2 :     STD_LOGIC_VECTOR(31 downto 0);


signal 	Result_ready,clear_ADC_flags :     STD_LOGIC;
signal	ADC_busy :     STD_LOGIC;

signal DPRAM_ADDR_RST : std_logic;

signal  test_sig :     STD_LOGIC_VECTOR(31 downto 0);

component PCI_SLAVE
  port (
    CLK                 : IN     STD_LOGIC;
    RESET               : IN     STD_LOGIC;
    REGS_RW_DAT_READ    : IN     STD_LOGIC_VECTOR(31 downto 0);
    REGS_RW_DAT_WRITE   : OUT    STD_LOGIC_VECTOR(31 downto 0);
    REGS_RW_ADDR        : OUT    STD_LOGIC_VECTOR(4 downto 0);
    REGS_RW_WREN        : OUT    STD_LOGIC;
    REGS_R_DAT_READ     : IN     STD_LOGIC_VECTOR(31 downto 0);
    REGS_R_ADDR         : OUT    STD_LOGIC_VECTOR(4 downto 0);
    DPRAM0_RW_DAT_READ  : IN     STD_LOGIC_VECTOR(31 downto 0);
    DPRAM0_RW_DAT_WRITE : OUT    STD_LOGIC_VECTOR(31 downto 0);
    DPRAM0_RW_ADDR      : OUT    STD_LOGIC_VECTOR(6 downto 0);
    DPRAM0_RW_WREN      : OUT    STD_LOGIC;
    DPRAM1_R_DAT_READ   : IN     STD_LOGIC_VECTOR(31 downto 0);
    DPRAM1_R_ADDR       : OUT    STD_LOGIC_VECTOR(6 downto 0);
    DPRAM2_R_DATA       : IN     STD_LOGIC_VECTOR(31 downto 0);
    DPRAM2_R_ADDR       : OUT    STD_LOGIC_VECTOR(10 downto 0);
    DPRAM3_R_DATA       : IN     STD_LOGIC_VECTOR(31 downto 0);
    DPRAM3_R_ADDR       : OUT    STD_LOGIC_VECTOR(10 downto 0);
    DPRAM_ADDR_RST      : IN     STD_LOGIC;
    PCI_FRAMEn          : IN     STD_LOGIC;
    PCI_BEn             : IN     STD_LOGIC_VECTOR(1 downto 0);
    PCI_IRDYn           : IN     STD_LOGIC;
    PCI_TRDYn           : buffer STD_LOGIC;
    PCI_INTn            : OUT    STD_LOGIC;
    PCI_AD              : INOUT  STD_LOGIC_VECTOR(15 downto 0);
    INT_IN              : IN     STD_LOGIC;
    TEST1               : OUT    STD_LOGIC_VECTOR(31 downto 0);
    TEST2               : OUT    STD_LOGIC_VECTOR(31 downto 0));
end component;




signal reset_data_set : std_logic;
signal data_set_count : std_logic_vector (4 downto 0);

--***********************************************************************************************************************************************
--*********************************************		    Signal analyser		*********************************************************
--***********************************************************************************************************************************************


component analyser
  port (
    clk               : in  std_logic;
    reset             : in  std_logic;
    ANA_record_len    : in  std_logic_vector(9 downto 0);
    ANA_addr_pointer  : out std_logic_vector(9 downto 0);
    ANA_RD_addr       : in  std_logic_vector(10 downto 0);
    ANA_RD_DAT        : out std_logic_vector(31 downto 0);
    ANA_slope         : in  std_logic;
    ANA_ARM           : in  std_logic;
    ANA_timer_en      : in  std_logic;
    ANA_DATA_ACQUIRED : out std_logic;
    ANA_ARMED         : out std_logic;
    ANA_trig          : in  std_logic_vector(7 downto 0);
    data_0            : in  std_logic_vector(31 downto 0);
    data_1            : in  std_logic_vector(31 downto 0);
    data_2            : in  std_logic_vector(31 downto 0);
    data_3            : in  std_logic_vector(31 downto 0);
    ANA_trig_src      : in  std_logic_vector(2 downto 0);
    ANA_CH1_src       : in  std_logic_vector(1 downto 0);
    ANA_CH2_src       : in  std_logic_vector(1 downto 0);
    ANA_timer         : in  std_logic_vector(23 downto 0);
    ANA_delay         : in  std_logic_vector(31 downto 0);
    ANA_tick_out      : out std_logic);
end component;



signal ANA_record_len    : std_logic_vector(9 downto 0);
signal ANA_addr_pointer  : std_logic_vector(9 downto 0);
signal ANA_RD_addr       : std_logic_vector(10 downto 0);
signal ANA_RD_DAT        : std_logic_vector(31 downto 0);
signal ANA_slope         : std_logic;
signal ANA_ARM           : std_logic;
signal ANA_timer_en      : std_logic;
signal ANA_DATA_ACQUIRED : std_logic;
signal ANA_ARMED         : std_logic;
signal ANA_trig          : std_logic_vector(7 downto 0);
signal data_0            : std_logic_vector(31 downto 0);
signal data_1            : std_logic_vector(31 downto 0);
signal data_2            : std_logic_vector(31 downto 0);
signal data_3            : std_logic_vector(31 downto 0);
signal ANA_trig_src      : std_logic_vector(2 downto 0);
signal ANA_CH1_src       : std_logic_vector(1 downto 0);
signal ANA_CH2_src       : std_logic_vector(1 downto 0);
signal ANA_timer         : std_logic_vector(23 downto 0);
signal ANA_delay         : std_logic_vector(31 downto 0);
signal ANA_tick_out      : std_logic;

constant glitch_capt : integer := 13;
signal	data_pulse_capt : std_logic_vector(glitch_capt-1 downto 0);
signal 	ANA_DAT : std_logic_vector(glitch_capt-1 downto 0);
  
BEGIN


--***********************************************************************************************************************************************
--********************************************* 	  PCI SLAVE intefrace mapping   	*********************************************************
--***********************************************************************************************************************************************

INT_IN <= '0';

  PCI_SLAVE_1: PCI_SLAVE
    port map (
      CLK                 => PCI_CLK,
      RESET               => RESET,
      REGS_RW_DAT_READ    => REGS_RW_DAT_READ,
      REGS_RW_DAT_WRITE   => REGS_RW_DAT_WRITE,
      REGS_RW_ADDR        => REGS_RW_ADDR,
      REGS_RW_WREN        => REGS_RW_WREN,
      REGS_R_DAT_READ     => REGS_R_DAT_READ,
      REGS_R_ADDR         => REGS_R_ADDR,
      DPRAM0_RW_DAT_READ  => x"00000000",
      DPRAM0_RW_DAT_WRITE => open,
      DPRAM0_RW_ADDR      => open,
      DPRAM0_RW_WREN      => open,
      DPRAM1_R_DAT_READ   => DPRAM_D,--adc buffer data
--debug
--debug
--debug
      --DPRAM1_R_DAT_READ   => x"12345678",--adc buffer data  
--debug
--debug
--debug
      DPRAM1_R_ADDR		  => DPRAM_A(6 downto 0),--adc buffer address
      DPRAM2_R_DATA       => x"00000000",
      DPRAM2_R_ADDR       => open,
      DPRAM3_R_DATA       => x"00000000",
      DPRAM3_R_ADDR       => open,
      DPRAM_ADDR_RST      => DPRAM_ADDR_RST,
      PCI_FRAMEn          => PCI_FRAMEn,
      PCI_BEn             => PCI_BEn,
      PCI_IRDYn           => PCI_IRDYn,
      PCI_TRDYn           => PCI_TRDYn,
      PCI_INTn            => PCI_INTn,
      PCI_AD              => PCI_AD,
      INT_IN              => INT_IN,
      TEST1               => test_sig,
      TEST2               => open);


pci_test<= test_sig(7 downto 0);


--***********************************************************************************************************************************************
--********************************************* 		  status bit generation		   **********************************************************
--***********************************************************************************************************************************************

		
process(CLK, reset)
begin
if rising_edge(CLK) then
	if reset = '1' then
		Result_ready <= '0';
		ADC_busy <= '0';
	elsif measurement_done = '1' then
		Result_ready <= '1';
		ADC_busy <= '0';
	elsif sample = '1' then
		ADC_busy <= '1';
	elsif clear_ADC_flags = '1' then
		Result_ready <= '0';
		ADC_busy <= '0';
	end if;
end if;	
end process;


--***********************************************************************************************************************************************
--*********************************************		    Registers PCI read/write		*********************************************************
--***********************************************************************************************************************************************


--RW registers write
process(PCI_CLK, reset)
begin
if rising_edge(PCI_CLK) then
	if REGS_RW_WREN = '1' then

	VME_RW_registers (TO_INTEGER(UNSIGNED(REGS_RW_ADDR))) <=  REGS_RW_DAT_WRITE; 
	end if;
end if;	
end process;
--RW registers read	
	REGS_RW_DAT_READ <= VME_RW_registers (TO_INTEGER(UNSIGNED(REGS_RW_ADDR)));
	
--R registers read
	REGS_R_DAT_READ	<= VME_R_registers (TO_INTEGER(UNSIGNED(REGS_R_ADDR)));


--***********************************************************************************************************************************************
--*********************************************		    measurement result write		*********************************************************
--***********************************************************************************************************************************************




Wr_Regs : PROCESS  (  reset, PCI_CLK )
BEGIN
  IF   reset = '1' THEN

	    VME_R_registers(0)     <= (OTHERS => '0');      
	    VME_R_registers(1)     <= (OTHERS => '0');
	    VME_R_registers(2)     <= (OTHERS => '0');
	    VME_R_registers(3)     <= (OTHERS => '0');
	    VME_R_registers(4)     <= (OTHERS => '0');      
--	    VME_R_registers(5)     <= (OTHERS => '0');
--	    VME_R_registers(6)     <= (OTHERS => '0');
--	    VME_R_registers(7)     <= (OTHERS => '0');    
	    VME_R_registers(8)     <= (OTHERS => '0');
	    VME_R_registers(9)     <= (OTHERS => '0');
	    VME_R_registers(10)     <= (OTHERS => '0');
	    VME_R_registers(11)     <= (OTHERS => '0');      
	    VME_R_registers(12)     <= (OTHERS => '0');
	    VME_R_registers(13)     <= (OTHERS => '0');
	    VME_R_registers(14)     <= (OTHERS => '0');
	    VME_R_registers(15)     <= (OTHERS => '0');

  ELSIF  Rising_edge ( PCI_CLK) THEN


	
	end if;
end process;	

--	regs_rw_sel --0x0000
--	regs_r_sel  --0x0080
--	dpram0_sel 	--0x0100
--	dpram1_sel  --0x0180
--	dpram2_sel  --0x0200
--	dpram3_sel  --0x0280
	

--***********************************************************************************************************************************************
--*********************************************			   RW registers mapping			*********************************************************
--***********************************************************************************************************************************************

--control registers	
--0x0000
	clear_ADC_flags <= VME_RW_registers(0)(0);	
	ARM <= VME_RW_registers(0)(1);
	software_trigger <= VME_RW_registers(0)(2);
	sampling_clk_source <= VME_RW_registers(0)(3);
	trig_select <= VME_RW_registers(0)(4);
	
	sampling_freq <= VME_RW_registers(1)(15 downto 0); --0x0004	
	num_of_measurements <= VME_RW_registers(2)(15 downto 0); --0x0008
	
	--0x000C
	Single_Channel_Mode_Channel_number <= VME_RW_registers(3)(9 downto 4);
	Single_Channel_Mode <= VME_RW_registers(3)(0);
	
	--0x000F
	DPRAM_A(11 downto 7) <= VME_RW_registers(4)(4 downto 0);
	
	

--status registers
	
	VME_R_registers(5)(0) <= Result_ready;
	VME_R_registers(5)(1) <= ADC_busy;
	VME_R_registers(5)(2) <= armed;
	VME_R_registers(5)(3) <= measurement_done;
	VME_R_registers(5)(4) <= '1';
	
	
--***********************************************************************************************************************************************
--*********************************************	 relays and LEDs mapping				*********************************************************
--***********************************************************************************************************************************************



	
	
	STAT_LED(0) <= VME_RW_registers(0)(0); --clear_ADC_flags;
	STAT_LED(1) <= VME_RW_registers(0)(1); --ARM
	STAT_LED(2) <= VME_RW_registers(0)(2); --software_trigger
	STAT_LED(3) <= VME_RW_registers(0)(3); --sampling_clk_source
	STAT_LED(4) <= VME_R_registers(5)(0); --result_ready;
	STAT_LED(5) <= VME_R_registers(5)(1); --ADC_busy
	STAT_LED(6) <= VME_R_registers(5)(2); --armed
	STAT_LED(7) <= VME_R_registers(5)(3); --measurement_done
	





	
END REGISTERS_architecture;
