library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity clkdivider is
  generic (
    divider : integer := 2);  -- number of clocks to generate enable pulse
  
  port (
    clk       : in  std_logic;          -- general clock
    reset     : in  std_logic;          -- async reset
    clkenable : out std_logic);  -- clock enable used to turn on the clock

end clkdivider;

architecture v1 of clkdivider is
begin  -- v1
-- purpose: counts down to zero and when at zero, then it generates clkenable pulse which is exactly 1 tick lock
-- type   : sequential
-- inputs : clk, reset
count: process (clk, reset)
  variable counter : integer range divider downto 0;
                                        -- counter stuff
begin  -- process count
  if reset = '0' then                   -- asynchronous reset (active low)
    counter := divider;                 -- set the state to the divider val.
  elsif clk'event and clk = '0' then    -- rising clock edge
    counter := counter - 1;             -- decrease counts
    if counter = 0 then
          counter := divider;
	  clkenable <= '1';
	else
	  clkenable <= '0';
    end if;
  end if;
end process count;

end v1; 
