library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use work.Types.all;

entity vme_bridge is
  
  port (
    -- general part:
    resetn       : in  std_logic;        -- reset input, asynchronous
    clk         : in  std_logic;        -- 50MHz clk input
    -- vme64x part:
    xdata       : inout std_logic_vector(31 downto 0);  -- vme data bus
    xaddr       : in  std_logic_vector(23 downto 1);  -- vme address bus
    xam         : in  std_logic_vector(5 downto 0);  -- vme address modifier
    xbufdir     : out std_logic;        -- vme buffer direction register
    xiackoutn   : out std_logic;        -- interrupt acknowledge output
    xiackinn    : in  std_logic;        -- interrupt ack input
    xiackn      : in  std_logic;        -- interrupt acknowledge
    xas         : in  std_logic;        -- vme address strobe
    xlwordn     : in  std_logic;        -- lword of vme
    xdsn        : in  std_logic_vector(1 downto 0);  -- data strobes
    xwriten     : in  std_logic;        -- write from vme
    xdtack      : out std_logic;        -- vme data acknowledge
    xbufoen     : out std_logic_vector(1 downto 0);        -- vme buffers output enable
    xirq        : out std_logic;  -- interrupt requesters
    xsysreset   : in std_logic;        -- sysfail request out
    -- cpld only stuff:
    adrsel      : in  std_logic_vector(7 downto 0);  -- address selector headers
                                                        -- put on cpld header conn.

    -- test output:
    C_EXT    : out std_logic_vector(9 downto 1);  -- for testing. to be erased later on
    
	--reserved lines
	CPLD_CLK :  in  std_logic;  -- 212MHz clock
	RSV3 : out  std_logic;  
	RSV1 : out  std_logic;  --devsel
	
	CPU_INT : out std_logic;
	RVD1  : in  std_logic;
	RVD0  : in  std_logic;
	RVD11  : in  std_logic;
	RVD13  : in  std_logic;
	RVD12  : in  std_logic;
	test_lines : out  std_logic_vector(31 downto 16); 
	
	PCI_CLK : out std_logic;
	

	
	
	Main_CK_enable : out std_logic;
	

    -- spi interface for accessing the EEPROM configuration memory + serial
    -- number chip
    spi_CS       : IN std_logic;           -- SPI slave select
    SPI_SI      : in  std_logic;           -- master in. We are master
    SPI_SO      : out std_logic;           -- master out
    SPI_SCK       : in std_logic;           -- we provide clock        

    
   
 -- fpga configuration stuff:

    CPLD_prog_nCONFIG  : out std_logic;        -- active serial nconfig
    CPLD_PROG_nCE      : out std_logic;        -- activeserial chip enable for fpga
    CPLD_prog_CONF_DONE  : in std_logic;        -- activeserial CONF_DONE
    CPLD_prog_DCLK     : out std_logic;        -- activeserial clock
    CPLD_prog_DATA     : in std_logic;      	-- activeserial output
    CPLD_prog_ASDI     : out std_logic;        -- activeserial dataout
    CPLD_prog_nCS      : out std_logic;        -- activeserial ncso


    reconfig  : in std_logic; 
    CPLD_STAT : out std_logic;  -- LED on the front panel

    FPGA_RESET  : out std_logic;       -- reset fpga signal
 
 --  PCI-like multiplexed communication
  -- address/data bus is 16 bit wide, BE0,BE1 are used as data strobes and command lines like in PCI
    FPGA_IRDYn      	: out   std_logic;   -- CPLD not ready
    FPGA_TRDYn      	: in    std_logic;   -- FPGA not ready
    FPGA_FRAMEn     	: out   std_logic;   -- start of transfer
    FPGA_AD         	: inout std_logic_vector(15 downto 0);       -- muletiplexed PCI-like address and data
    FPGA_BEn      	: out   std_logic_vector(1 downto 0);    	 -- word strobes / command: 01- read, 11 - write
    FPGA_INTn	: in 	std_logic	--interrupt
	);
end vme_bridge;

architecture V1 of vme_bridge is
-------------------------------------------------------------------------------
-- component definitions:
-------------------------------------------------------------------------------
  
  -- generic vme interface
  component VME_CONTROLLER
    port (
      reset        : in    std_logic;
      CLK          : in    std_logic;
      v_am         : IN    STD_LOGIC_VECTOR(5 downto 0);
      n_v_ds       : IN    STD_LOGIC_VECTOR(1 downto 0);
      n_v_as       : IN    STD_LOGIC;
      n_v_lw       : IN    STD_LOGIC;
      n_v_iackin   : IN    STD_LOGIC;
      n_v_write    : IN    STD_LOGIC;
      n_v_sys_res  : IN    STD_LOGIC;
      v_dtack      : OUT   STD_LOGIC;
      v_berr       : OUT   STD_LOGIC;
      n_v_irq      : OUT   STD_LOGIC;
      n_v_iackout  : OUT   STD_LOGIC;
      v_ddir       : OUT   STD_LOGIC;
      n_v_doe      : OUT   STD_LOGIC_VECTOR(1 downto 0);
      va           : IN    STD_LOGIC_VECTOR(23 downto 1);
      vd           : INOUT STD_LOGIC_VECTOR(31 downto 0);
      ModuleAddr   : in    std_logic_vector(7 downto 0);
      spi_CS       : in    std_logic;
      SPI_SI       : in    std_logic;
      SPI_SO       : out   std_logic;
      SPI_CLK      : in    std_logic;
      SPI_INT      : out   std_logic;
      EXT_out      : OUT   STD_LOGIC_VECTOR(9 downto 1);
	  test_out     : OUT   STD_LOGIC_VECTOR(31 downto 16);
      fpga_nconfig : out   std_logic;
      fpga_nce     : out   std_logic;
      as_asdo      : out   std_logic;
      as_data      : in    std_logic;
      as_dclk      : out   std_logic;
      as_ncs       : out   std_logic;
      IRDYn        : out   std_logic;
      TRDYn        : in    std_logic;
      FRAMEn       : out   std_logic;
      AD           : inout std_logic_vector(15 downto 0);
      BEn          : out   std_logic_vector(1 downto 0);
      INTn         : in    std_logic);
  end component;

-------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------

  signal 	interrupts,
			reset,
			vbufdir,
			vdtack : std_logic;  -- just placeholder for irqs
						
	signal vbufoen : std_logic_vector(1 downto 0);
	signal vme_test : std_logic_vector(7 downto 0);
  
begin 

  -----------------------------------------------------------------------------
  -- VME component instances:
  -----------------------------------------------------------------------------

  -- NOTE: FOR THE MOMENT THE INTERRUPT ENABLE IS DISABLED!!!!!!

                 reset <= not resetn;
                 FPGA_RESET <= reset;
                 
                 VME_CONTROLLER_1: VME_CONTROLLER
                   port map (
                     reset        => reset,
                     CLK          => CLK,
                     --vme signals
                     v_am         => xam,
                     n_v_ds       => xdsn,
                     n_v_as       => xas,
                     n_v_lw       => xlwordn,
                     n_v_iackin   => xiackinn,
                     n_v_write    => xwriten,
                     n_v_sys_res  => xsysreset,
                     v_dtack      => vdtack,
                     v_berr       => open,
                     n_v_irq      => xirq,
                     n_v_iackout  => xiackoutn,
                     v_ddir       => vbufdir,
                     n_v_doe      => vbufoen,
                     va           => xaddr,
                     vd           => xdata,                     
                     ModuleAddr   => not adrsel,
                     --SPI signals
                     spi_CS       => spi_CS,
                     SPI_SI       => SPI_SI,
                     SPI_SO       => SPI_SO,
                     SPI_CLK      => SPI_SCK,
                     SPI_INT      => CPU_INT,
                     
                     EXT_out(8 downto 1)      => C_EXT(8 downto 1),
					 test_out     => test_lines,
                     --fpga config signals
                     fpga_nconfig => open,
                     fpga_nce     => open,
                     as_asdo      => open,
                     as_data      => '0',
                     as_dclk      => open,
                     as_ncs       => open,
                     --PCI signals
                     IRDYn        => FPGA_IRDYn,
                     TRDYn        => FPGA_TRDYn,
                     FRAMEn       => FPGA_FRAMEn,
                     AD           => FPGA_AD,
                     BEn          => FPGA_BEn,
                     INTn         => FPGA_INTn);

--for debugging purposes - reading from OUT port (buffer type generates warnings)
xbufoen <= vbufoen;
xbufdir <= vbufdir;
xdtack <= vdtack;

    CPLD_prog_nCONFIG  <= 'Z';
    CPLD_PROG_nCE      <= 'Z';
    CPLD_prog_DCLK       <= 'Z';    
    CPLD_prog_ASDI       <= 'Z';
    CPLD_prog_nCS   <= 'Z';


-----------------------------------------------------------------------------
  -- I/O assignments:
-----------------------------------------------------------------------------



   -- C_EXT(9 downto 2) <= (others => 'Z'); 
    --C_EXT(9 downto 2) <= adrsel; 
    CPLD_STAT <= 'Z';
	--reserved lines
--	CPLD_CLK <= 'Z';  -- 212MHz clock
	RSV3 <= SPI_SI;
	RSV1 <=  SPI_SCK ;
	--CPU_INT <= 'Z';
	--RVD1  <= 'Z';
	--RVD0  <= 'Z';
	--RVD11  <= 'Z';
	--RVD13  <= 'Z';
	--RVD12  <= 'Z';
	PCI_CLK <= 'Z';
	Main_CK_enable <= '1';
	
--	test_lines(31 downto 16) <= (others => 'Z');
--	test_lines(31 downto 16)<= FPGA_AD(15 downto 0);
	--test_lines(31 downto 16)<= xdata(15 downto 0);
--	test_lines(27 downto 24) <= vme_test(3 downto 0);
--	test_lines(25 downto 24)  <= vbufoen ;
--	test_lines(26)  <= vbufdir ;
--	test_lines(27)  <= vdtack ;
--	test_lines(28)  <= xwriten ;
--	test_lines(29)  <=	xas;
--	test_lines(31 downto 30)  <= xdsn(1 downto 0);
--	test_lines(23 downto 16)<= xdata(23 downto 16);
	

end V1;
