library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

package types is
  
  -- std_logic_vector types - start with V
  subtype VWord is std_logic_vector(15 downto 0);  -- 16 bit word
  subtype VQWord is std_logic_vector(23 downto 0);  -- 24 bit vector
  subtype SQWord is signed(23 downto 0);  -- 24bit signed to use in arithmetics
  subtype SWord is signed(15 downto 0);  -- 16 bit signed stuff
  subtype SByte is signed(7 downto 0);  -- 8 bit signed
  subtype VByte is std_logic_vector(7 downto 0);  -- 8 bit unsigned vector
  subtype VLong is std_logic_vector(31 downto 0);  -- 32bit register
  -- integer types start with I
  subtype IUINT8 is integer range 0 to 255;  -- integer range
  subtype IUINT4 is integer range 0 to 15;   -- 4 bit integer
  subtype IADCAddr is integer range 6 downto 0;   -- ADC address to read
  subtype IQWord is integer range 0 to 16777215;  -- 24 bits integer
  subtype ISQWord is integer range -8388608 to 8388607;  -- signed 24 bits number

  -- array of vectors start with AV
  type AVADCMEM is array (5 downto 0) of SWord;  -- ADC memory registers
  type AVACCUMULATOR is array (5 downto 0) of SQWord;  -- averager
  type AIACCUMULATOR is array (5 downto 0) of ISQWord;  -- integer averager
  type AVADCOFS is array (5 downto 0) of SWord;  -- ADC offsets
  type SHAREDREGISTERS is array (NATURAL range <>) of VLong;

end types;
