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 ######  ##  ##  ##  ##     ##    ##       ######### 
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################################################################################
# NOTE by Maciej Lipinski
# This UCF file was inherited from the EDA-02299-V2-VXS-Switch project
# 1) first all commeted lines were removed
# 2) then all unneeded lines were commented out)
# 3) then some stuff was added
#
################################################################################
NET "VCXO_MHZ20" CLOCK_DEDICATED_ROUTE = FALSE;

# Pinning for GTP122 tile
# INST "C456/X0Y0_GTPDual/gtp_dual_i" LOC = GTP_DUAL_X0Y0;
# INST "C457/IBUFGDS_inst" LOC = BUFDS_X0Y0;

# NET "FPGA2VXS0_N" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS0_N" LOC = AL2;
# NET "FPGA2VXS0_P" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS0_P" LOC = AK2;
# NET "FPGA2VXS1_N" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS1_N" LOC = AN3;
# NET "FPGA2VXS1_P" IOSTANDARD = LVPECL_25;
# NET "FPGA2VXS1_P" LOC = AN4;
# NET "GTP122_CLK_N" LOC = AL4;
# NET "GTP122_CLK_P" LOC = AL5;
# NET "GTP122_CLK_N" IOSTANDARD = LVPECL_25;
# NET "GTP122_CLK_P" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA0_N" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA0_N" LOC = AM1;
# NET "VXS2FPGA0_P" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA0_P" LOC = AL1;
# NET "VXS2FPGA1_N" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA1_N" LOC = AP2;
# NET "VXS2FPGA1_P" IOSTANDARD = LVPECL_25;
# NET "VXS2FPGA1_P" LOC = AP3;

# Pinning for GTP118 tile (Added for V2)
INST "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/U_GTP_TILE_INST/gtp_dual_i" LOC = GTP_DUAL_X0Y1;
INST "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_ibufgds_gtp" LOC = BUFDS_X0Y1;

NET "FPGA2SFP_N" IOSTANDARD = LVPECL_25;
NET "FPGA2SFP_N" LOC = AH2;
NET "FPGA2SFP_P" IOSTANDARD = LVPECL_25;
NET "FPGA2SFP_P" LOC = AJ2;

NET "FPGA2VXS2_N" IOSTANDARD = LVPECL_25;
NET "FPGA2VXS2_N" LOC = AE2;
NET "FPGA2VXS2_P" IOSTANDARD = LVPECL_25;
NET "FPGA2VXS2_P" LOC = AD2;

NET "GTP118_CLK_N" LOC = AF3;
NET "GTP118_CLK_P" LOC = AF4;
NET "GTP118_CLK_N" IOSTANDARD = LVPECL_25;
NET "GTP118_CLK_P" IOSTANDARD = LVPECL_25;
NET "SFP2FPGA_N" IOSTANDARD = LVPECL_25;
NET "SFP2FPGA_N" LOC = AG1;
NET "SFP2FPGA_P" IOSTANDARD = LVPECL_25;
NET "SFP2FPGA_P" LOC = AH1;

NET "VXS2FPGA2_N" IOSTANDARD = LVPECL_25;
NET "VXS2FPGA2_N" LOC = AF1;
NET "VXS2FPGA2_P" IOSTANDARD = LVPECL_25;
NET "VXS2FPGA2_P" LOC = AE1;

# Clocking

# NET "FPGA_MHZ100_N" LOC = AG16;

# NET "FPGA_MHZ100_P" LOC = AH17;
# NET "FPGA_MHZ100_N" IOSTANDARD = LVDS_25;
# NET "FPGA_MHZ100_P" IOSTANDARD = LVDS_25;
# NET "FPGA_MHZ200_N" LOC = AG15;
# NET "FPGA_MHZ200_P" LOC = AH15;
# NET "FPGA_MHZ200_N" IOSTANDARD = LVPECL_25;
# NET "FPGA_MHZ200_P" IOSTANDARD = LVPECL_25;
# NET "FPGA_MHZ50_N" LOC = AG17;
# NET "FPGA_MHZ50_P" LOC = AH18;
# NET "FPGA_MHZ50_N" IOSTANDARD = LVDS_25;
# NET "FPGA_MHZ50_P" IOSTANDARD = LVDS_25;
# NET "RF_CLK_FPGA_N" LOC = AG13;
# NET "RF_CLK_FPGA_P" LOC = AH12;
# NET "RF_CLK_FPGA_N" IOSTANDARD = LVPECL_25;
# NET "RF_CLK_FPGA_P" IOSTANDARD = LVPECL_25;
# NET "TAG_FPGA_N" LOC = AH13;
# NET "TAG_FPGA_P" LOC = AH14;
# NET "TAG_FPGA_N" IOSTANDARD = LVPECL_25;
# NET "TAG_FPGA_P" IOSTANDARD = LVPECL_25;
NET "VCXO_MHZ125_N" LOC = AH19;
NET "VCXO_MHZ125_P" LOC = AH20;
NET "VCXO_MHZ125_N" IOSTANDARD = LVPECL_25;
NET "VCXO_MHZ125_P" IOSTANDARD = LVPECL_25;
NET "VCXO_MHZ20" IOSTANDARD = LVCMOS33;
NET "VCXO_MHZ20" LOC = H20;

# General I/O
# NET "ACE_TCK_O" IOSTANDARD = LVCMOS33;
# NET "ACE_TCK_O" LOC = AN33;
# NET "ACE_TDI_O" IOSTANDARD = LVCMOS33;
# NET "ACE_TDI_O" LOC = AN34;
NET "ACE_TDO_I" IOSTANDARD = LVCMOS33;
NET "ACE_TDO_I" LOC = AM32;
# NET "ACE_TMS_O" IOSTANDARD = LVCMOS33;
# NET "ACE_TMS_O" LOC = AN32;
NET "DAC_PLL125_SYNC_N" IOSTANDARD = LVCMOS33;
NET "DAC_PLL125_SYNC_N" LOC = AM13;
NET "DAC_PLL20_SYNC_N" IOSTANDARD = LVCMOS33;
NET "DAC_PLL20_SYNC_N" LOC = AN13;
NET "DAC_PLL_DIN" IOSTANDARD = LVCMOS33;
NET "DAC_PLL_DIN" LOC = AM12;
NET "DAC_PLL_SCLK" IOSTANDARD = LVCMOS33;
NET "DAC_PLL_SCLK" LOC = AL11;
NET "DQ" IOSTANDARD = LVCMOS33;
NET "DQ" LOC = L4;
# NET "FPGA_IO_OUT2" IOSTANDARD = LVCMOS33;
# NET "FPGA_IO_OUT2" LOC = AK9;
NET "FPGA_IO_OUT1" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_OUT1" LOC = AK8;
NET "FP_JTAG_ENA_N" IOSTANDARD = LVCMOS33;
NET "FP_JTAG_ENA_N" LOC = AP32;
NET "FRAMCS_N" IOSTANDARD = LVCMOS33;
NET "FRAMCS_N" LOC = W34;
NET "FRAMMISO" IOSTANDARD = LVCMOS33;
NET "FRAMMISO" LOC = V33;
NET "FRAMMOSI" IOSTANDARD = LVCMOS33;
NET "FRAMMOSI" LOC = V32;
NET "FRAMSCLK" IOSTANDARD = LVCMOS33;
NET "FRAMSCLK" LOC = Y32;
NET "FRAMWPDIS" IOSTANDARD = LVCMOS33;
NET "FRAMWPDIS" LOC = W32;
NET "FRAMWP_N" IOSTANDARD = LVCMOS33;
NET "FRAMWP_N" LOC = V34;
NET "GAP_N" IOSTANDARD = LVCMOS33;
NET "GAP_N" LOC = C34;
NET "GA_N[0]" IOSTANDARD = LVCMOS33;
NET "GA_N[0]" LOC = C33;
NET "GA_N[1]" IOSTANDARD = LVCMOS33;
NET "GA_N[1]" LOC = B33;
NET "GA_N[2]" IOSTANDARD = LVCMOS33;
NET "GA_N[2]" LOC = B32;
NET "GA_N[3]" IOSTANDARD = LVCMOS33;
NET "GA_N[3]" LOC = C32;
NET "GA_N[4]" IOSTANDARD = LVCMOS33;
NET "GA_N[4]" LOC = D32;
NET "HWVERSION[0]" IOSTANDARD = LVCMOS33;
NET "HWVERSION[0]" LOC = AK7;
NET "HWVERSION[1]" IOSTANDARD = LVCMOS33;
NET "HWVERSION[1]" LOC = AJ7;
NET "HWVERSION[2]" IOSTANDARD = LVCMOS33;
NET "HWVERSION[2]" LOC = AH7;
NET "HWVERSION[3]" IOSTANDARD = LVCMOS33;
NET "HWVERSION[3]" LOC = AG7;
# NET "KEEPER" IOSTANDARD = LVCMOS33;
# NET "KEEPER" LOC = T6;
NET "LED_CLK_G" IOSTANDARD = LVCMOS33;
NET "LED_CLK_G" LOC = AJ31;
NET "LED_CLK_R" IOSTANDARD = LVCMOS33;
NET "LED_CLK_R" LOC = AK31;
NET "LED_SFP_SCL" IOSTANDARD = LVCMOS33;
NET "LED_SFP_SCL" LOC = AB33;
NET "LED_SFP_SDA" IOSTANDARD = LVCMOS33;
NET "LED_SFP_SDA" LOC = AC33;
# NET "LED_SPARE_G" IOSTANDARD = LVCMOS33;
# NET "LED_SPARE_G" LOC = AH30;
# NET "LED_SPARE_R" IOSTANDARD = LVCMOS33;
# NET "LED_SPARE_R" LOC = AJ30;
NET "POR" IOSTANDARD = LVCMOS33;
NET "POR" LOC = AG23;
# NET "POWERDOWN" IOSTANDARD = LVCMOS33;
# NET "POWERDOWN" LOC = E6;
NET "PP10_SCL" IOSTANDARD = LVCMOS33;
NET "PP10_SCL" LOC = L34;
NET "PP10_SDA" IOSTANDARD = LVCMOS33;
NET "PP10_SDA" LOC = T33;
NET "PP11_SCL" IOSTANDARD = LVCMOS33;
NET "PP11_SCL" LOC = R34;
NET "PP11_SDA" IOSTANDARD = LVCMOS33;
NET "PP11_SDA" LOC = R33;
NET "PP12_SCL" IOSTANDARD = LVCMOS33;
NET "PP12_SCL" LOC = R32;
NET "PP12_SDA" IOSTANDARD = LVCMOS33;
NET "PP12_SDA" LOC = T34;
# NET "PP1_SCL_I" IOSTANDARD = LVCMOS33;
# NET "PP1_SCL_I" LOC = J34;
# NET "PP1_SCL_O_N" IOSTANDARD = LVCMOS33;
# NET "PP1_SCL_O_N" LOC = H34;
NET "PP1_SDA_I" IOSTANDARD = LVCMOS33;
NET "PP1_SDA_I" LOC = H33;
# NET "PP1_SDA_O_N" IOSTANDARD = LVCMOS33;
# NET "PP1_SDA_O_N" LOC = J32;
NET "PP2_SCL" IOSTANDARD = LVCMOS33;
NET "PP2_SCL" LOC = H32;
NET "PP2_SDA" IOSTANDARD = LVCMOS33;
NET "PP2_SDA" LOC = K34;
NET "PP3_SCL" IOSTANDARD = LVCMOS33;
NET "PP3_SCL" LOC = G33;
NET "PP3_SDA" IOSTANDARD = LVCMOS33;
NET "PP3_SDA" LOC = G32;
NET "PP4_SCL" IOSTANDARD = LVCMOS33;
NET "PP4_SCL" LOC = K32;
NET "PP4_SDA" IOSTANDARD = LVCMOS33;
NET "PP4_SDA" LOC = K33;
NET "PP5_SCL" IOSTANDARD = LVCMOS33;
NET "PP5_SCL" LOC = F34;
NET "PP5_SDA" IOSTANDARD = LVCMOS33;
NET "PP5_SDA" LOC = F33;
NET "PP6_SCL" IOSTANDARD = LVCMOS33;
NET "PP6_SCL" LOC = N32;
NET "PP6_SDA" IOSTANDARD = LVCMOS33;
NET "PP6_SDA" LOC = P32;
NET "PP7_SCL" IOSTANDARD = LVCMOS33;
NET "PP7_SCL" LOC = N34;
NET "PP7_SDA" IOSTANDARD = LVCMOS33;
NET "PP7_SDA" LOC = P34;
NET "PP8_SCL" IOSTANDARD = LVCMOS33;
NET "PP8_SCL" LOC = M32;
NET "PP8_SDA" IOSTANDARD = LVCMOS33;
NET "PP8_SDA" LOC = L33;
NET "PP9_SCL" IOSTANDARD = LVCMOS33;
NET "PP9_SCL" LOC = M33;
NET "PP9_SDA" IOSTANDARD = LVCMOS33;
NET "PP9_SDA" LOC = N33;
# NET "Q_CS_N" IOSTANDARD = LVCMOS33;
#  NET "Q_CS_N" LOC = AP14;
NET "Q_MISO" IOSTANDARD = LVCMOS33;
NET "Q_MISO" LOC = AN14;
# NET "Q_MOSI" IOSTANDARD = LVCMOS33;
# NET "Q_MOSI" LOC = AN12;
# NET "Q_SCLK" IOSTANDARD = LVCMOS33;
# NET "Q_SCLK" LOC = AP12;
#: NET "SEL_VXS" IOSTANDARD = LVCMOS33;
#: "SEL_VXS" LOC = AM11;
NET "SFP0_LOS" IOSTANDARD = LVCMOS33;
NET "SFP0_LOS" LOC = AM33;
NET "SFP0_PRSNT_N" IOSTANDARD = LVCMOS33;
NET "SFP0_PRSNT_N" LOC = AL33;
NET "SFP0_SCL" IOSTANDARD = LVCMOS33;
NET "SFP0_SCL" LOC = AL34;
NET "SFP0_SDA" IOSTANDARD = LVCMOS33;
NET "SFP0_SDA" LOC = AK32;
# NET "SFP0_TX_DIS" IOSTANDARD = LVCMOS33;
# NET "SFP0_TX_DIS" LOC = AK33;
NET "SFP1_LOS" IOSTANDARD = LVCMOS33;
NET "SFP1_LOS" LOC = AJ32;
NET "SFP1_PRSNT_N" IOSTANDARD = LVCMOS33;
NET "SFP1_PRSNT_N" LOC = AH32;
NET "SFP1_SCL" IOSTANDARD = LVCMOS33;
NET "SFP1_SCL" LOC = AG32;
NET "SFP1_SDA" IOSTANDARD = LVCMOS33;
NET "SFP1_SDA" LOC = AK34;
# NET "SFP1_TX_DIS" IOSTANDARD = LVCMOS33;
# NET "SFP1_TX_DIS" LOC = AH33;
NET "SFP2_LOS" IOSTANDARD = LVCMOS33;
NET "SFP2_LOS" LOC = AJ34;
NET "SFP2_PRSNT_N" IOSTANDARD = LVCMOS33;
NET "SFP2_PRSNT_N" LOC = AH34;
NET "SFP2_SCL" IOSTANDARD = LVCMOS33;
NET "SFP2_SCL" LOC = AE34;
NET "SFP2_SDA" IOSTANDARD = LVCMOS33;
NET "SFP2_SDA" LOC = AF34;
NET "SFP2_TX_DIS" IOSTANDARD = LVCMOS33;
NET "SFP2_TX_DIS" LOC = AE33;
NET "SFP3_LOS" IOSTANDARD = LVCMOS33;
NET "SFP3_LOS" LOC = AD34;
NET "SFP3_PRSNT_N" IOSTANDARD = LVCMOS33;
NET "SFP3_PRSNT_N" LOC = AC34;
NET "SFP3_SCL" IOSTANDARD = LVCMOS33;
NET "SFP3_SCL" LOC = Y34;
NET "SFP3_SDA" IOSTANDARD = LVCMOS33;
NET "SFP3_SDA" LOC = AA34;
NET "SFP3_TX_DIS" IOSTANDARD = LVCMOS33;
NET "SFP3_TX_DIS" LOC = AA33;
# NET "SW_RX_N" LOC = F28;
# NET "SW_RX_IBUFDS/SW_RX_P" LOC = E28;
# NET "SW_RX_P" LOC = E28;
# NET "SW_RX_N" IOSTANDARD = LVPECL_25;
# NET "SW_RX_P" IOSTANDARD = LVPECL_25;
NET "SW_SE1" IOSTANDARD = LVCMOS33;
NET "SW_SE1" LOC = E34;
NET "SW_SE2" IOSTANDARD = LVCMOS33;
NET "SW_SE2" LOC = E29;
NET "SW_SE3" IOSTANDARD = LVCMOS33;
NET "SW_SE3" LOC = F29;
NET "SW_SE4" IOSTANDARD = LVCMOS33;
NET "SW_SE4" LOC = F30;
NET "SW_SE5" IOSTANDARD = LVCMOS33;
NET "SW_SE5" LOC = D34;
NET "SW_SE6" IOSTANDARD = LVCMOS33;
NET "SW_SE6" LOC = E32;
NET "SW_SE7" IOSTANDARD = LVCMOS33;
NET "SW_SE7" LOC = E33;
NET "SW_SE8" IOSTANDARD = LVCMOS33;
NET "SW_SE8" LOC = G30;
# NET "SW_TX_N" IOSTANDARD = LVPECL_25;
# NET "SW_TX_N" LOC = G28;
# NET "SW_TX_P" LOC = H28;
# NET "SW_TX_P" IOSTANDARD = LVPECL_25;
NET "SYSRST_N" IOSTANDARD = LVCMOS33;
NET "SYSRST_N" LOC = A33;



####### test ports used for WR ############
####### old definitions

#used for 1-wire
#NET "TESTPORT[1]" IOSTANDARD = LVCMOS33;
#NET "TESTPORT[1]" LOC = Y7;

#used for UART RXD
#NET "TESTPORT[2]" IOSTANDARD = LVCMOS33;
#NET "TESTPORT[2]" LOC = AB5;

# unused
#NET "TESTPORT[3]" IOSTANDARD = LVCMOS33;
#NET "TESTPORT[3]" LOC = AA5;

# used for UART TXD
#NET "TESTPORT[4]" IOSTANDARD = LVCMOS33;
#NET "TESTPORT[4]" LOC = AB7;

# unused
#NET "TESTPORT[5]" IOSTANDARD = LVCMOS33;
#NET "TESTPORT[5]" LOC = AB6;

################# new definitions
# UART at TESTPORT[0]
NET "UART_RXD" IOSTANDARD = LVCMOS33;
NET "UART_RXD" LOC = AA6;

# 1-wire at TESTPORT[1]
NET "DQ_WR" IOSTANDARD = LVCMOS33;
NET "DQ_WR" LOC = Y7;
NET "DQ_WR" PULLUP;

# UART at TESTPORT[2]
NET "UART_TXD" IOSTANDARD = LVCMOS33;
NET "UART_TXD" LOC = AB5;



##########################################################

# NET "TESTPORT[10]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[10]" LOC = AD6;
# NET "TESTPORT[11]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[11]" LOC = AD5;
# NET "TESTPORT[12]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[12]" LOC = AD7;
# NET "TESTPORT[13]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[13]" LOC = AE6;
# NET "TESTPORT[14]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[14]" LOC = AF6;
# NET "TESTPORT[15]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[15]" LOC = AF5;


# NET "TESTPORT[6]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[6]" LOC = AC5;

# NET "TESTPORT[7]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[7]" LOC = AC4;
# NET "TESTPORT[8]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[8]" LOC = AD4;
# NET "TESTPORT[9]" IOSTANDARD = LVCMOS33;
# NET "TESTPORT[9]" LOC = AC7;
NET "XBAR_ADDR[0]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[0]" LOC = H8;
NET "XBAR_ADDR[1]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[1]" LOC = G10;
NET "XBAR_ADDR[2]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[2]" LOC = J10;
NET "XBAR_ADDR[3]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[3]" LOC = H10;
NET "XBAR_ADDR[4]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[4]" LOC = G12;
NET "XBAR_ADDR[5]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[5]" LOC = G8;
NET "XBAR_ADDR[6]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[6]" LOC = F10;
NET "XBAR_ADDR[7]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[7]" LOC = F8;
NET "XBAR_ADDR[8]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[8]" LOC = E8;
NET "XBAR_ADDR[9]" IOSTANDARD = LVCMOS33;
NET "XBAR_ADDR[9]" LOC = D10;
NET "XBAR_CS_N" IOSTANDARD = LVCMOS33;
NET "XBAR_CS_N" LOC = E12;
NET "XBAR_DATA[0]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[0]" LOC = K8;
NET "XBAR_DATA[1]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[1]" LOC = J9;
NET "XBAR_DATA[2]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[2]" LOC = H9;
NET "XBAR_DATA[3]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[3]" LOC = K9;
NET "XBAR_DATA[4]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[4]" LOC = E13;
NET "XBAR_DATA[5]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[5]" LOC = E11;
NET "XBAR_DATA[6]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[6]" LOC = D12;
NET "XBAR_DATA[7]" IOSTANDARD = LVCMOS33;
NET "XBAR_DATA[7]" LOC = E9;
NET "XBAR_DIS_N" IOSTANDARD = LVCMOS33;
NET "XBAR_DIS_N" LOC = L10;
NET "XBAR_DS_N" IOSTANDARD = LVCMOS33;
NET "XBAR_DS_N" LOC = F9;
# NET "XBAR_ENRX_N[0]" IOSTANDARD = LVCMOS33;
# NET "XBAR_ENRX_N[0]" LOC = B12;
# NET "XBAR_ENRX_N[1]" IOSTANDARD = LVCMOS33;
# NET "XBAR_ENRX_N[1]" LOC = F11;
# NET "XBAR_ENTX_N[0]" IOSTANDARD = LVCMOS33;
# NET "XBAR_ENTX_N[0]" LOC = C12;
# NET "XBAR_ENTX_N[1]" IOSTANDARD = LVCMOS33;
# NET "XBAR_ENTX_N[1]" LOC = G11;
NET "XBAR_LOS" IOSTANDARD = LVCMOS33;
NET "XBAR_LOS" LOC = L11;
NET "XBAR_PERROR[0]" IOSTANDARD = LVCMOS33;
NET "XBAR_PERROR[0]" LOC = B13;
NET "XBAR_PERROR[1]" IOSTANDARD = LVCMOS33;
NET "XBAR_PERROR[1]" LOC = J11;
NET "XBAR_RD" IOSTANDARD = LVCMOS33;
NET "XBAR_RD" LOC = D11;
NET "XBAR_RSTRX_N[0]" IOSTANDARD = LVCMOS33;
NET "XBAR_RSTRX_N[0]" LOC = A13;
NET "XBAR_RSTRX_N[1]" IOSTANDARD = LVCMOS33;
NET "XBAR_RSTRX_N[1]" LOC = F13;
NET "XBAR_RST_N" IOSTANDARD = LVCMOS33;
NET "XBAR_RST_N" LOC = C13;
# NET "XBAR_SER" IOSTANDARD = LVCMOS33;
# NET "XBAR_SER" LOC = K11;
NET "XBAR_SET_N" IOSTANDARD = LVCMOS33;
NET "XBAR_SET_N" LOC = G13;

# Missing pull-up resistors in HW V1
NET "GAP_N" PULLUP;
NET "GA_N[0]" PULLUP;
NET "GA_N[1]" PULLUP;
NET "GA_N[2]" PULLUP;
NET "GA_N[3]" PULLUP;
NET "GA_N[4]" PULLUP;


# PlanAhead Generated physical constraints
NET "FPGA_IO_E1_N" LOC = AK11; # AL10
NET "FPGA_IO_E2_N" LOC = AL10; # AK11
NET "FPGA_IO_IN1" LOC = AG8;   # AJ11
NET "FPGA_IO_IN2" LOC = AH9;   # AJ10
NET "FPGA_IO_Z1" LOC = AJ9;
NET "FPGA_IO_Z2" LOC = AH8;

# PlanAhead Generated IO constraints
NET "FPGA_IO_E1_N" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_E2_N" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_IN1" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_IN2" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_Z1" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_Z2" IOSTANDARD = LVCMOS33;
NET "FPGA_IO_E1_N" DRIVE = 12;
NET "FPGA_IO_E2_N" DRIVE = 12;
NET "FPGA_IO_IN1" DRIVE = 12;
NET "FPGA_IO_IN2" DRIVE = 12;
NET "FPGA_IO_Z1" DRIVE = 12;
NET "FPGA_IO_Z2" DRIVE = 12;
NET "FPGA_IO_E1_N" SLEW = SLOW;
NET "FPGA_IO_E2_N" SLEW = SLOW;
NET "FPGA_IO_IN1" SLEW = SLOW;
NET "FPGA_IO_IN2" SLEW = SLOW;
NET "FPGA_IO_Z1" SLEW = SLOW;
NET "FPGA_IO_Z2" SLEW = SLOW;

############################ WR stuff #################################
# DDMTD
NET "VCXO_MHZ20" TNM_NET = VCXO_MHZ20;

# ML-replaced
# TIMESPEC TS_VCXO_MHZ20 = PERIOD "VCXO_MHZ20" 21 MHz HIGH 50%;
TIMESPEC TS_VCXO_MHZ20 = PERIOD "VCXO_MHZ20" 50 ns HIGH 50%;

# main
NET "VCXO_MHZ125_N" TNM_NET = VCXO_MHZ125_N;

# ML-replaced
# TIMESPEC TS_VCXO_MHZ125_N = PERIOD "VCXO_MHZ125_N" 132 MHz HIGH 50%;
TIMESPEC TS_VCXO_MHZ125_N = PERIOD "VCXO_MHZ125_N" 8 ns HIGH 50%;

NET "VCXO_MHZ125_P" TNM_NET = VCXO_MHZ125_P;

# ML-replaced
# TIMESPEC TS_VCXO_MHZ125_P = PERIOD "VCXO_MHZ125_P" 132 MHz HIGH 50%;
TIMESPEC TS_VCXO_MHZ125_P = PERIOD "VCXO_MHZ125_P" 8 ns HIGH 50%;

# SFP:
NET "GTP118_CLK_N" TNM_NET = GTP118_CLK_N;

# ML-replaced
#TIMESPEC TS_GTP118_CLK_N = PERIOD "GTP118_CLK_N" 132 MHz HIGH 50%;
TIMESPEC TS_GTP118_CLK_N = PERIOD "GTP118_CLK_N" 8 ns HIGH 50%;

NET "GTP118_CLK_P" TNM_NET = GTP118_CLK_P;

# ML-replaced
#TIMESPEC TS_GTP118_CLK_P = PERIOD "GTP118_CLK_P" 132 MHz HIGH 50%;
TIMESPEC TS_GTP118_CLK_P = PERIOD "GTP118_CLK_P" 8 ns HIGH 50%;

NET "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch0_rx_rec_clk_pad" TNM_NET = cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch0_rx_rec_clk_pad;
TIMESPEC TS_cmp_xwrc_board_vxs_cmp_xwrc_platform_gen_phy_virtex5_cmp_gtp_ch0_rx_rec_clk_pad = PERIOD "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch0_rx_rec_clk_pad" 8 ns HIGH 50%;

NET "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad" TNM_NET = cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad;
TIMESPEC TS_cmp_xwrc_board_vxs_cmp_xwrc_platform_gen_phy_virtex5_cmp_gtp_ch1_rx_rec_clk_pad = PERIOD "cmp_xwrc_board_vxs/cmp_xwrc_platform/gen_phy_virtex5.cmp_gtp/ch1_rx_rec_clk_pad" 8 ns HIGH 50%;


INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;


TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;

###############################################################################

#Created by Constraints Editor (xc5vlx50t-ff1136-1) - 2015/04/09
# NET "FPGA_MHZ100_P" TNM_NET = FPGA_MHZ100_P;
# TIMESPEC TS_FPGA_MHZ100_P = PERIOD "FPGA_MHZ100_P" 105 MHz HIGH 50%;

# NET "GTP122_CLK_P" TNM_NET = GTP122_CLK_P;
# TIMESPEC TS_GTP122_CLK_P = PERIOD "GTP122_CLK_P" 105 MHz HIGH 50%;
# NET "RF_CLK_FPGA_P" TNM_NET = RF_CLK_FPGA_P;
# TIMESPEC TS_RF_CLK_FPGA_P = PERIOD "RF_CLK_FPGA_P" 105 MHz HIGH 50%;

#Created by Constraints Editor (xc5vlx50t-ff1136-1) - 2015/04/13
# NET "FPGA_MHZ100_N" TNM_NET = FPGA_MHZ100_N;
# TIMESPEC TS_FPGA_MHZ100_N = PERIOD "FPGA_MHZ100_N" 105 MHz HIGH 50%;

# NET "GTP122_CLK_N" TNM_NET = GTP122_CLK_N;
# TIMESPEC TS_GTP122_CLK_N = PERIOD "GTP122_CLK_N" 105 MHz HIGH 50%;
# NET "RF_CLK_FPGA_N" TNM_NET = RF_CLK_FPGA_N;
# TIMESPEC TS_RF_CLK_FPGA_N = PERIOD "RF_CLK_FPGA_N" 105 MHz HIGH 50%;
#NET "C456/REFCLKOUT_X0Y0" TNM_NET = C456/REFCLKOUT_X0Y0;
#TIMESPEC TS_C456_REFCLKOUT_X0Y0 = PERIOD "C456/REFCLKOUT_X0Y0" 132 MHz HIGH 50%;
