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-- Title          : Wishbone slave core for WR aux sma output generation module
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-- File           : sma_config_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from sma_config.wb
-- Created        : Mon Oct 17 22:55:06 2022
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE sma_config.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package sma_config_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_sma_config_in_registers is record
    sma0_mux_i                               : std_logic_vector(7 downto 0);
    sma1_mux_i                               : std_logic_vector(7 downto 0);
    cus_prh_i                                : std_logic_vector(28 downto 0);
    cus_prl_i                                : std_logic_vector(28 downto 0);
    cus_csr_i                                : std_logic_vector(28 downto 0);
    pps_prh_i                                : std_logic_vector(28 downto 0);
    pps_csr_i                                : std_logic_vector(28 downto 0);
    utc_csr_i                                : std_logic_vector(28 downto 0);
    sma0_fdly_i                              : std_logic_vector(8 downto 0);
    sma1_fdly_i                              : std_logic_vector(8 downto 0);
    end record;
  
  constant c_sma_config_in_registers_init_value: t_sma_config_in_registers := (
    sma0_mux_i => (others => '0'),
    sma1_mux_i => (others => '0'),
    cus_prh_i => (others => '0'),
    cus_prl_i => (others => '0'),
    cus_csr_i => (others => '0'),
    pps_prh_i => (others => '0'),
    pps_csr_i => (others => '0'),
    utc_csr_i => (others => '0'),
    sma0_fdly_i => (others => '0'),
    sma1_fdly_i => (others => '0')
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_sma_config_out_registers is record
      sma0_mux_o                               : std_logic_vector(7 downto 0);
      sma0_mux_load_o                          : std_logic;
      sma1_mux_o                               : std_logic_vector(7 downto 0);
      sma1_mux_load_o                          : std_logic;
      cus_prh_o                                : std_logic_vector(28 downto 0);
      cus_prh_load_o                           : std_logic;
      cus_prl_o                                : std_logic_vector(28 downto 0);
      cus_prl_load_o                           : std_logic;
      cus_csr_o                                : std_logic_vector(28 downto 0);
      cus_csr_load_o                           : std_logic;
      pps_prh_o                                : std_logic_vector(28 downto 0);
      pps_prh_load_o                           : std_logic;
      pps_csr_o                                : std_logic_vector(28 downto 0);
      pps_csr_load_o                           : std_logic;
      utc_csr_o                                : std_logic_vector(28 downto 0);
      utc_csr_load_o                           : std_logic;
      sma0_fdly_o                              : std_logic_vector(8 downto 0);
      sma0_fdly_load_o                         : std_logic;
      sma1_fdly_o                              : std_logic_vector(8 downto 0);
      sma1_fdly_load_o                         : std_logic;
      end record;
    
    constant c_sma_config_out_registers_init_value: t_sma_config_out_registers := (
      sma0_mux_o => (others => '0'),
      sma0_mux_load_o => '0',
      sma1_mux_o => (others => '0'),
      sma1_mux_load_o => '0',
      cus_prh_o => (others => '0'),
      cus_prh_load_o => '0',
      cus_prl_o => (others => '0'),
      cus_prl_load_o => '0',
      cus_csr_o => (others => '0'),
      cus_csr_load_o => '0',
      pps_prh_o => (others => '0'),
      pps_prh_load_o => '0',
      pps_csr_o => (others => '0'),
      pps_csr_load_o => '0',
      utc_csr_o => (others => '0'),
      utc_csr_load_o => '0',
      sma0_fdly_o => (others => '0'),
      sma0_fdly_load_o => '0',
      sma1_fdly_o => (others => '0'),
      sma1_fdly_load_o => '0'
      );
    function "or" (left, right: t_sma_config_in_registers) return t_sma_config_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body sma_config_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_sma_config_in_registers) return t_sma_config_in_registers is
variable tmp: t_sma_config_in_registers;
begin
tmp.sma0_mux_i := f_x_to_zero(left.sma0_mux_i) or f_x_to_zero(right.sma0_mux_i);
tmp.sma1_mux_i := f_x_to_zero(left.sma1_mux_i) or f_x_to_zero(right.sma1_mux_i);
tmp.cus_prh_i := f_x_to_zero(left.cus_prh_i) or f_x_to_zero(right.cus_prh_i);
tmp.cus_prl_i := f_x_to_zero(left.cus_prl_i) or f_x_to_zero(right.cus_prl_i);
tmp.cus_csr_i := f_x_to_zero(left.cus_csr_i) or f_x_to_zero(right.cus_csr_i);
tmp.pps_prh_i := f_x_to_zero(left.pps_prh_i) or f_x_to_zero(right.pps_prh_i);
tmp.pps_csr_i := f_x_to_zero(left.pps_csr_i) or f_x_to_zero(right.pps_csr_i);
tmp.utc_csr_i := f_x_to_zero(left.utc_csr_i) or f_x_to_zero(right.utc_csr_i);
tmp.sma0_fdly_i := f_x_to_zero(left.sma0_fdly_i) or f_x_to_zero(right.sma0_fdly_i);
tmp.sma1_fdly_i := f_x_to_zero(left.sma1_fdly_i) or f_x_to_zero(right.sma1_fdly_i);
return tmp;
end function;
end package body;
