#*****************************************************************************************
# Vivado (TM) v2019.2 (64-bit)
#
# diot_wr_mpsoc.tcl: Tcl script for re-creating project 'diot_wr_mpsoc'
#
# Generated by Vivado on Thu May 06 11:52:12 CEST 2021
# IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
#   original project, however they will not be launched automatically. To regenerate the
#   run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
#       following files are added to the source control system:-
#
# 1. This project restoration tcl script (diot_wr_mpsoc.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
#    "/home/greg/wr/wr-cores/syn/diot_wr_mpsoc/diot_wr_mpsoc.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd"
#
# 3. The following remote source files that were added to the original project:-
#
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.vh"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gthe4_channel_wrapper.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_bit_sync.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_v1_7_gthe4_channel.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_sync.v"
#    "/home/greg/wr/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/timing/dmtd_phase_meas.vhd"
#    "/home/greg/wr/wr-cores/modules/timing/dmtd_sampler.vhd"
#    "/home/greg/wr/wr-cores/modules/timing/dmtd_with_deglitcher.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/wr_fabric_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_path.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_path.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrcore_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/streamers_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_sync.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_sync_register.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_dacs/spec_serial_dac.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"
#    "/home/greg/wr/wr-cores/board/common/wr_board_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wr_core.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/wr_endpoint.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_diags_wb.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_periph.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/xwr_core.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd"
#    "/home/greg/wr/wr-cores/board/common/xwrc_board_common.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/xwrc_platform_vivado.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwrf_mux.vhd"
#    "/home/greg/wr/wr-cores/board/diot-sb/wrc_board_diot_simple.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
#    "/home/greg/wr/wr-cores/board/pxie-fmc/wr_pxie_fmc_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/dropping_buffer.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/escape_detector.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/escape_inserter.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd"
#    "/home/greg/wr/wr-cores/modules/timing/pulse_stamper.vhd"
#    "/home/greg/wr/wr-cores/modules/timing/pulse_stamper_sync.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/ts_restore_tai.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xrx_streamer.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xtx_streamer.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwb_fabric_sink.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwb_fabric_source.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xwr_streamers.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"
#    "/home/greg/wr/wr-cores/top/diot_wr_mpsoc/diot_wr_mpsoc.xdc"
#
#*****************************************************************************************

# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."

# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
  set origin_dir $::origin_dir_loc
}

# Set the project name
set _xil_proj_name_ "diot_wr_mpsoc"

# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
  set _xil_proj_name_ $::user_project_name
}

variable script_file
set script_file "diot_wr_mpsoc.tcl"

# Help information for this script
proc print_help {} {
  variable script_file
  puts "\nDescription:"
  puts "Recreate a Vivado project from this script. The created project will be"
  puts "functionally equivalent to the original project for which this script was"
  puts "generated. The script contains commands for creating a project, filesets,"
  puts "runs, adding/importing sources and setting properties on various objects.\n"
  puts "Syntax:"
  puts "$script_file"
  puts "$script_file -tclargs \[--origin_dir <path>\]"
  puts "$script_file -tclargs \[--project_name <name>\]"
  puts "$script_file -tclargs \[--help\]\n"
  puts "Usage:"
  puts "Name                   Description"
  puts "-------------------------------------------------------------------------"
  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
  puts "                       origin_dir path value is \".\", otherwise, the value"
  puts "                       that was set with the \"-paths_relative_to\" switch"
  puts "                       when this script was generated.\n"
  puts "\[--project_name <name>\] Create project with the specified name. Default"
  puts "                       name is the name of the project from where this"
  puts "                       script was generated.\n"
  puts "\[--help\]               Print help information for this script"
  puts "-------------------------------------------------------------------------\n"
  exit 0
}

if { $::argc > 0 } {
  for {set i 0} {$i < $::argc} {incr i} {
    set option [string trim [lindex $::argv $i]]
    switch -regexp -- $option {
      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
      "--help"         { print_help }
      default {
        if { [regexp {^-} $option] } {
          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
          return 1
        }
      }
    }
  }
}

# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/"]"

# Create project
create_project ${_xil_proj_name_} . -part xczu7cg-ffvf1517-1-e

# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]

# Set project properties
set obj [current_project]
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "part" -value "xczu7cg-ffvf1517-1-e" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_language" -value "VHDL" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "13" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "13" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "13" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "13" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "13" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "13" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "13" -objects $obj

# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
  create_fileset -srcset sources_1
}

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.vh"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gthe4_channel_wrapper.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_bit_sync.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_v1_7_gthe4_channel.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_sync.v"] \
 [file normalize "${origin_dir}/../../modules/wr_tbi_phy/disparity_gen_pkg.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/timing/dmtd_phase_meas.vhd"] \
 [file normalize "${origin_dir}/../../modules/timing/dmtd_sampler.vhd"] \
 [file normalize "${origin_dir}/../../modules/timing/dmtd_with_deglitcher.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/fabric/wr_fabric_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/endpoint_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_registers_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/endpoint_private_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_1000basex_pcs.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_autonegotiation.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_crc32_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_leds_controller.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_packet_filter.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_rtu_header_extract.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_rx_buffer.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_rx_crc_size_check.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_rx_early_address_match.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_rx_oob_insert.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_rx_path.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_rx_vlan_unit.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_rx_wb_master.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_sync_detect.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_sync_detect_16bit.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_timestamping_unit.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_ts_counter.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_tx_crc_inserter.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_tx_header_processor.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_tx_packet_injection.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_tx_path.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_tx_vlan_unit.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/ep_wishbone_controller.vhd"] \
 [file normalize "${origin_dir}/../../modules/wrc_core/wrc_syscon_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wrc_core/wrc_diags_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_softpll_ng/softpll_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wrc_core/wrcore_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/streamers_pkg.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_sync.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_sync_register.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"] \
 [file normalize "${origin_dir}/../../modules/fabric/xwrf_loopback/lbk_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_mini_nic/minic_wb_slave.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_pps_gen/pps_gen_wb.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_dacs/spec_serial_dac.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_dacs/spec_serial_dac_arb.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_softpll_ng/spll_aligner.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_softpll_ng/spll_wb_slave.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"] \
 [file normalize "${origin_dir}/../../board/common/wr_board_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wrc_core/wr_core.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/wr_endpoint.vhd"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_mini_nic/wr_mini_nic.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_pps_gen/wr_pps_gen.vhd"] \
 [file normalize "${origin_dir}/../../platform/xilinx/wr_xilinx_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_softpll_ng/wr_softpll_ng.vhd"] \
 [file normalize "${origin_dir}/../../modules/wrc_core/wrc_diags_wb.vhd"] \
 [file normalize "${origin_dir}/../../modules/wrc_core/wrc_syscon_wb.vhd"] \
 [file normalize "${origin_dir}/../../modules/wrc_core/wrc_periph.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"] \
 [file normalize "${origin_dir}/../../modules/wrc_core/xwr_core.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_endpoint/xwr_endpoint.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_mini_nic/xwr_mini_nic.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_pps_gen/xwr_pps_gen.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_softpll_ng/xwr_softpll_ng.vhd"] \
 [file normalize "${origin_dir}/../../board/common/xwrc_board_common.vhd"] \
 [file normalize "${origin_dir}/../../modules/wrc_core/xwrc_diags_wb.vhd"] \
 [file normalize "${origin_dir}/../../platform/xilinx/xwrc_platform_vivado.vhd"] \
 [file normalize "${origin_dir}/../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd"] \
 [file normalize "${origin_dir}/../../modules/fabric/xwrf_mux.vhd"] \
 [file normalize "${origin_dir}/../../board/diot-sb/wrc_board_diot_simple.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"] \
 [file normalize "${origin_dir}/../../board/pxie-fmc/wr_pxie_fmc_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/dropping_buffer.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/escape_detector.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/escape_inserter.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/fifo_showahead_adapter.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/streamers_priv_pkg.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/fixed_latency_ts_match.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/fixed_latency_delay.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd"] \
 [file normalize "${origin_dir}/../../modules/timing/pulse_stamper.vhd"] \
 [file normalize "${origin_dir}/../../modules/timing/pulse_stamper_sync.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/ts_restore_tai.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/wr_streamers_wb.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/xrtx_streamers_stats.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/xrx_streamer.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/xrx_streamers_stats.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/xtx_streamer.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/xtx_streamers_stats.vhd"] \
 [file normalize "${origin_dir}/../../modules/fabric/xwb_fabric_sink.vhd"] \
 [file normalize "${origin_dir}/../../modules/fabric/xwb_fabric_source.vhd"] \
 [file normalize "${origin_dir}/../../modules/wr_streamers/xwr_streamers.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd"] \
 [file normalize "${origin_dir}/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"] \
]
add_files -norecurse -fileset $obj $files

# Import local files from the original project
#GD set files [list \
#GD  [file normalize "${origin_dir}/diot_wr_mpsoc.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd" ]\
#GD ]
#GD set imported_files [import_files -fileset sources_1 $files]

# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj

set file "$origin_dir/../../modules/wr_tbi_phy/disparity_gen_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/timing/dmtd_phase_meas.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/timing/dmtd_sampler.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/timing/dmtd_with_deglitcher.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/fabric/wr_fabric_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/endpoint_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_registers_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/endpoint_private_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_1000basex_pcs.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_autonegotiation.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_crc32_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_leds_controller.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_packet_filter.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_rtu_header_extract.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_rx_buffer.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_rx_crc_size_check.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_rx_early_address_match.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_rx_oob_insert.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_rx_path.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_rx_vlan_unit.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_rx_wb_master.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_sync_detect.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_sync_detect_16bit.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_timestamping_unit.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_ts_counter.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_tx_crc_inserter.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_tx_header_processor.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_tx_packet_injection.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_tx_path.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_tx_vlan_unit.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/ep_wishbone_controller.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wrc_core/wrc_syscon_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wrc_core/wrc_diags_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_softpll_ng/softpll_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wrc_core/wrcore_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/streamers_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_sync.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_sync_register.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/fabric/xwrf_loopback/lbk_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_mini_nic/minic_wb_slave.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_pps_gen/pps_gen_wb.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_dacs/spec_serial_dac.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_dacs/spec_serial_dac_arb.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_softpll_ng/spll_aligner.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_softpll_ng/spll_wb_slave.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj

set file "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj

set file "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj

set file "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj

set file "$origin_dir/../../board/common/wr_board_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wrc_core/wr_core.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/wr_endpoint.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj

set file "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj

set file "$origin_dir/../../modules/wr_mini_nic/wr_mini_nic.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_pps_gen/wr_pps_gen.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../platform/xilinx/wr_xilinx_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_softpll_ng/wr_softpll_ng.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wrc_core/wrc_diags_wb.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wrc_core/wrc_syscon_wb.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wrc_core/wrc_periph.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wrc_core/xwr_core.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_endpoint/xwr_endpoint.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_mini_nic/xwr_mini_nic.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_pps_gen/xwr_pps_gen.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_softpll_ng/xwr_softpll_ng.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../board/common/xwrc_board_common.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wrc_core/xwrc_diags_wb.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../platform/xilinx/xwrc_platform_vivado.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/fabric/xwrf_mux.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../board/diot-sb/wrc_board_diot_simple.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "is_global_include" -value "1" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "is_global_include" -value "1" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "is_global_include" -value "1" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "is_global_include" -value "1" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "is_global_include" -value "1" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "is_global_include" -value "1" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "is_global_include" -value "1" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "is_global_include" -value "1" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "is_global_include" -value "1" -objects $file_obj

set file "$origin_dir/../../board/pxie-fmc/wr_pxie_fmc_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/dropping_buffer.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/escape_detector.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/escape_inserter.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/fifo_showahead_adapter.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/streamers_priv_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/fixed_latency_ts_match.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/fixed_latency_delay.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/timing/pulse_stamper.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/timing/pulse_stamper_sync.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/ts_restore_tai.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/wr_streamers_wb.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/xrtx_streamers_stats.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/xrx_streamer.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/xrx_streamers_stats.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/xtx_streamer.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/xtx_streamers_stats.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/fabric/xwb_fabric_sink.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/fabric/xwb_fabric_source.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../modules/wr_streamers/xwr_streamers.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj

set file "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "library" -value "work" -objects $file_obj


# Set 'sources_1' fileset file properties for local files
#GD set file "hdl/design_1_wrapper.vhd"
#GD set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
#GD set_property -name "file_type" -value "VHDL" -objects $file_obj

# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
#GD set_property -name "top" -value "design_1_wrapper" -objects $obj
#GD set_property -name "top_auto_set" -value "0" -objects $obj

# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
  create_fileset -constrset constrs_1
}

# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]

# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/../../top/diot_wr_mpsoc/diot_wr_mpsoc.xdc"]"
set file_added [add_files -norecurse -fileset $obj [list $file]]
set file "$origin_dir/../../top/diot_wr_mpsoc/diot_wr_mpsoc.xdc"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj

# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
set_property -name "target_part" -value "xczu7cg-ffvf1517-1-e" -objects $obj

# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
  create_fileset -simset sim_1
}

# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Empty (no sources present)

# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
#GD set_property -name "top" -value "design_1_wrapper" -objects $obj
#GD set_property -name "top_lib" -value "xil_defaultlib" -objects $obj

# Set 'utils_1' fileset object
set obj [get_filesets utils_1]
# Empty (no sources present)

# Set 'utils_1' fileset properties
set obj [get_filesets utils_1]


# Adding sources referenced in BDs, if not already added
if { [get_files jtag_cores.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
}
if { [get_files jtag_tap.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
}
if { [get_files lm32_include.vh] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.vh
}
if { [get_files lm32_adder.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
}
if { [get_files lm32_addsub.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
}
if { [get_files lm32_allprofiles.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
}
if { [get_files lm32_logic_op.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
}
if { [get_files lm32_multiplier.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
}
if { [get_files lm32_shifter.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
}
if { [get_files sockit_owm.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
}
if { [get_files gtwizard_ultrascale_2.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.v
}
if { [get_files gtwizard_ultrascale_2_gthe4_channel_wrapper.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
}
if { [get_files gtwizard_ultrascale_2_gtwizard_gthe4.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v
}
if { [get_files gtwizard_ultrascale_2_gtwizard_top.v] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v
}
if { [get_files gtwizard_ultrascale_v1_7_bit_sync.v] == "" } {
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}
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  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v
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  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_v1_7_gthe4_channel.v
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if { [get_files ep_rx_crc_size_check.vhd] == "" } {
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if { [get_files ep_rx_oob_insert.vhd] == "" } {
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if { [get_files ep_rx_wb_master.vhd] == "" } {
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if { [get_files ep_ts_counter.vhd] == "" } {
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if { [get_files ep_tx_inject_ctrl.vhd] == "" } {
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if { [get_files wrc_syscon_pkg.vhd] == "" } {
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if { [get_files wrc_diags_pkg.vhd] == "" } {
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if { [get_files wrcore_pkg.vhd] == "" } {
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if { [get_files streamers_pkg.vhd] == "" } {
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if { [get_files gc_pulse_synchronizer2.vhd] == "" } {
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if { [get_files gc_extend_pulse.vhd] == "" } {
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if { [get_files gc_frequency_meter.vhd] == "" } {
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if { [get_files gc_pulse_synchronizer.vhd] == "" } {
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}
if { [get_files gc_reset_multi_aasd.vhd] == "" } {
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}
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}
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if { [get_files gc_sync_ffs.vhd] == "" } {
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}
if { [get_files gc_sync_word_wr.vhd] == "" } {
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}
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}
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}
if { [get_files memory_loader_pkg.vhd] == "" } {
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}
if { [get_files generic_dpram.vhd] == "" } {
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}
if { [get_files generic_dpram_dualclock.vhd] == "" } {
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}
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}
if { [get_files generic_dpram_split.vhd] == "" } {
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}
if { [get_files generic_shiftreg_fifo.vhd] == "" } {
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}
if { [get_files generic_simple_dpram.vhd] == "" } {
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}
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}
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}
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}
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}
if { [get_files lbk_pkg.vhd] == "" } {
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}
if { [get_files lbk_wishbone_controller.vhd] == "" } {
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}
if { [get_files lm32_dp_ram.vhd] == "" } {
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}
if { [get_files lm32_ram.vhd] == "" } {
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}
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}
if { [get_files minic_wb_slave.vhd] == "" } {
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if { [get_files pps_gen_wb.vhd] == "" } {
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}
if { [get_files sdb_rom.vhd] == "" } {
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}
if { [get_files simple_uart_pkg.vhd] == "" } {
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}
if { [get_files simple_uart_wb.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
}
if { [get_files spec_serial_dac.vhd] == "" } {
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if { [get_files spec_serial_dac_arb.vhd] == "" } {
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if { [get_files spll_aligner.vhd] == "" } {
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}
if { [get_files spll_wbgen2_pkg.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
}
if { [get_files spll_wb_slave.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd
}
if { [get_files uart_async_rx.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
}
if { [get_files uart_async_tx.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
}
if { [get_files uart_baud_gen.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
}
if { [get_files wb_onewire_master.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
}
if { [get_files wb_simple_uart.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
}
if { [get_files wb_slave_adapter.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
}
if { [get_files wbgen2_eic.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
}
if { [get_files wbgen2_fifo_sync.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
}
if { [get_files whiterabbit_gtpe2_channel_wrapper.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd
}
if { [get_files whiterabbit_gtpe2_channel_wrapper_gt.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd
}
if { [get_files whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd
}
if { [get_files whiterabbit_gtxe2_channel_wrapper_gt.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd
}
if { [get_files wr_board_pkg.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/board/common/wr_board_pkg.vhd
}
if { [get_files wr_core.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wrc_core/wr_core.vhd
}
if { [get_files wr_endpoint.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wr_endpoint/wr_endpoint.vhd
}
if { [get_files wr_gthe4_phy_family7_xilinx_ip.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7_xilinx_ip.vhd
}
if { [get_files wr_gtp_phy_family7.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
}
if { [get_files wr_gtx_phy_family7.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
}
if { [get_files wr_mini_nic.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd
}
if { [get_files wr_pps_gen.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd
}
if { [get_files wr_xilinx_pkg.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd
}
if { [get_files wr_softpll_ng.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd
}
if { [get_files wrc_diags_wb.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wrc_core/wrc_diags_wb.vhd
}
if { [get_files wrc_syscon_wb.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd
}
if { [get_files wrc_periph.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wrc_core/wrc_periph.vhd
}
if { [get_files xwb_crossbar.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
}
if { [get_files xwb_dpram.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
}
if { [get_files xwb_lm32.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
}
if { [get_files xwb_onewire_master.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
}
if { [get_files xwb_sdb_crossbar.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
}
if { [get_files xwb_simple_uart.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
}
if { [get_files xwr_core.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wrc_core/xwr_core.vhd
}
if { [get_files xwr_endpoint.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd
}
if { [get_files xwr_mini_nic.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd
}
if { [get_files xwr_pps_gen.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd
}
if { [get_files xwr_softpll_ng.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd
}
if { [get_files xwrc_board_common.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/board/common/xwrc_board_common.vhd
}
if { [get_files xwrc_diags_wb.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd
}
if { [get_files xwrc_platform_vivado.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/platform/xilinx/xwrc_platform_vivado.vhd
}
if { [get_files xwrf_loopback.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd
}
if { [get_files xwrf_mux.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/modules/fabric/xwrf_mux.vhd
}
if { [get_files wrc_board_diot_simple.vhd] == "" } {
  import_files -quiet -fileset sources_1 /home/greg/wr/wr-cores/board/diot-sb/wrc_board_diot_simple.vhd
}


# Proc to create BD design_1
proc cr_bd_design_1 { parentCell } {
# The design that will be created by this Tcl proc contains the following 
# module references:
# wrc_board_diot_simple



  # CHANGE DESIGN NAME HERE
  set design_name design_1

  common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

  create_bd_design $design_name

  set bCheckIPsPassed 1
  ##################################################################
  # CHECK IPs
  ##################################################################
  set bCheckIPs 1
  if { $bCheckIPs == 1 } {
     set list_check_ips "\ 
  xilinx.com:ip:util_ds_buf:2.1\
  xilinx.com:ip:zynq_ultra_ps_e:3.3\
  "

   set list_ips_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }

   if { $list_ips_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }

  }

  ##################################################################
  # CHECK Modules
  ##################################################################
  set bCheckModules 1
  if { $bCheckModules == 1 } {
     set list_check_mods "\ 
  wrc_board_diot_simple\
  "

   set list_mods_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."

   foreach mod_vlnv $list_check_mods {
      if { [can_resolve_reference $mod_vlnv] == 0 } {
         lappend list_mods_missing $mod_vlnv
      }
   }

   if { $list_mods_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
      common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
      set bCheckIPsPassed 0
   }
}

  if { $bCheckIPsPassed != 1 } {
    common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
    return 3
  }

  variable script_folder

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports

  # Create ports
  set BOARD_SCL_0 [ create_bd_port -dir IO -from 0 -to 0 BOARD_SCL_0 ]
  set BOARD_SDA_0 [ create_bd_port -dir IO -from 0 -to 0 BOARD_SDA_0 ]
  set EEPROM_SCL [ create_bd_port -dir IO -from 0 -to 0 EEPROM_SCL ]
  set EEPROM_SDA_0 [ create_bd_port -dir IO -from 0 -to 0 EEPROM_SDA_0 ]
  set led_act_o_0 [ create_bd_port -dir O led_act_o_0 ]
  set led_link_o_0 [ create_bd_port -dir O led_link_o_0 ]
  set pll20dac_cs_n_o_0 [ create_bd_port -dir O pll20dac_cs_n_o_0 ]
  set pll25dac_cs_n_o_0 [ create_bd_port -dir O pll25dac_cs_n_o_0 ]
  set plldac_din_o_0 [ create_bd_port -dir O plldac_din_o_0 ]
  set plldac_sclk_o_0 [ create_bd_port -dir O plldac_sclk_o_0 ]
  set pps_led_o_0 [ create_bd_port -dir O pps_led_o_0 ]
  set pps_p_o_0 [ create_bd_port -dir O pps_p_o_0 ]
  set sfp_det_i_0 [ create_bd_port -dir I sfp_det_i_0 ]
  set sfp_los_i_0 [ create_bd_port -dir I sfp_los_i_0 ]
  set sfp_rxn_i_0 [ create_bd_port -dir I sfp_rxn_i_0 ]
  set sfp_rxp_i_0 [ create_bd_port -dir I sfp_rxp_i_0 ]
  set sfp_txn_o_0 [ create_bd_port -dir O sfp_txn_o_0 ]
  set sfp_txp_o_0 [ create_bd_port -dir O sfp_txp_o_0 ]
  set uart_rxd_i_0 [ create_bd_port -dir I uart_rxd_i_0 ]
  set uart_txd_o_0 [ create_bd_port -dir O uart_txd_o_0 ]
  set wr_clk_helper_62_5m_n_i_0 [ create_bd_port -dir I wr_clk_helper_62_5m_n_i_0 ]
  set wr_clk_helper_62_5m_p_i_0 [ create_bd_port -dir I wr_clk_helper_62_5m_p_i_0 ]
  set wr_clk_main_62_5m_n_i_0 [ create_bd_port -dir I wr_clk_main_62_5m_n_i_0 ]
  set wr_clk_main_62_5m_p_i_0 [ create_bd_port -dir I wr_clk_main_62_5m_p_i_0 ]
  set wr_clk_sfp_125m_n_i_0 [ create_bd_port -dir I wr_clk_sfp_125m_n_i_0 ]
  set wr_clk_sfp_125m_p_i_0 [ create_bd_port -dir I wr_clk_sfp_125m_p_i_0 ]

  # Create instance: util_ds_buf_0, and set properties
  set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0 ]
  set_property -dict [ list \
   CONFIG.C_BUF_TYPE {IOBUF} \
   CONFIG.C_SIZE {1} \
 ] $util_ds_buf_0

  # Create instance: util_ds_buf_1, and set properties
  set util_ds_buf_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_1 ]
  set_property -dict [ list \
   CONFIG.C_BUF_TYPE {IOBUF} \
   CONFIG.C_SIZE {1} \
 ] $util_ds_buf_1

  # Create instance: util_ds_buf_4, and set properties
  set util_ds_buf_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_4 ]
  set_property -dict [ list \
   CONFIG.C_BUF_TYPE {IOBUF} \
   CONFIG.C_SIZE {1} \
 ] $util_ds_buf_4

  # Create instance: util_ds_buf_5, and set properties
  set util_ds_buf_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_5 ]
  set_property -dict [ list \
   CONFIG.C_BUF_TYPE {IOBUF} \
   CONFIG.C_SIZE {1} \
 ] $util_ds_buf_5

  # Create instance: wrc_board_diot_simple_0, and set properties
  set block_name wrc_board_diot_simple
  set block_cell_name wrc_board_diot_simple_0
  if { [catch {set wrc_board_diot_simple_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $wrc_board_diot_simple_0 eq "" } {
     catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: zynq_ultra_ps_e_0, and set properties
  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
  set_property -dict [ list \
   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
   CONFIG.PSU_MIO_0_DIRECTION {out} \
   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
   CONFIG.PSU_MIO_0_POLARITY {Default} \
   CONFIG.PSU_MIO_10_DIRECTION {inout} \
   CONFIG.PSU_MIO_10_POLARITY {Default} \
   CONFIG.PSU_MIO_11_DIRECTION {inout} \
   CONFIG.PSU_MIO_11_POLARITY {Default} \
   CONFIG.PSU_MIO_12_DIRECTION {out} \
   CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
   CONFIG.PSU_MIO_12_POLARITY {Default} \
   CONFIG.PSU_MIO_13_DIRECTION {inout} \
   CONFIG.PSU_MIO_13_POLARITY {Default} \
   CONFIG.PSU_MIO_14_DIRECTION {inout} \
   CONFIG.PSU_MIO_14_POLARITY {Default} \
   CONFIG.PSU_MIO_15_DIRECTION {inout} \
   CONFIG.PSU_MIO_15_POLARITY {Default} \
   CONFIG.PSU_MIO_16_DIRECTION {inout} \
   CONFIG.PSU_MIO_16_POLARITY {Default} \
   CONFIG.PSU_MIO_17_DIRECTION {inout} \
   CONFIG.PSU_MIO_17_POLARITY {Default} \
   CONFIG.PSU_MIO_18_DIRECTION {inout} \
   CONFIG.PSU_MIO_18_POLARITY {Default} \
   CONFIG.PSU_MIO_19_DIRECTION {inout} \
   CONFIG.PSU_MIO_19_POLARITY {Default} \
   CONFIG.PSU_MIO_1_DIRECTION {inout} \
   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_1_POLARITY {Default} \
   CONFIG.PSU_MIO_1_SLEW {fast} \
   CONFIG.PSU_MIO_20_DIRECTION {inout} \
   CONFIG.PSU_MIO_20_POLARITY {Default} \
   CONFIG.PSU_MIO_21_DIRECTION {inout} \
   CONFIG.PSU_MIO_21_POLARITY {Default} \
   CONFIG.PSU_MIO_22_DIRECTION {out} \
   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
   CONFIG.PSU_MIO_22_POLARITY {Default} \
   CONFIG.PSU_MIO_26_DIRECTION {inout} \
   CONFIG.PSU_MIO_26_POLARITY {Default} \
   CONFIG.PSU_MIO_27_DIRECTION {inout} \
   CONFIG.PSU_MIO_27_POLARITY {Default} \
   CONFIG.PSU_MIO_28_DIRECTION {inout} \
   CONFIG.PSU_MIO_28_POLARITY {Default} \
   CONFIG.PSU_MIO_29_DIRECTION {inout} \
   CONFIG.PSU_MIO_29_POLARITY {Default} \
   CONFIG.PSU_MIO_2_DIRECTION {inout} \
   CONFIG.PSU_MIO_2_POLARITY {Default} \
   CONFIG.PSU_MIO_30_DIRECTION {inout} \
   CONFIG.PSU_MIO_30_POLARITY {Default} \
   CONFIG.PSU_MIO_31_DIRECTION {inout} \
   CONFIG.PSU_MIO_31_POLARITY {Default} \
   CONFIG.PSU_MIO_32_DIRECTION {inout} \
   CONFIG.PSU_MIO_32_POLARITY {Default} \
   CONFIG.PSU_MIO_33_DIRECTION {inout} \
   CONFIG.PSU_MIO_33_POLARITY {Default} \
   CONFIG.PSU_MIO_34_DIRECTION {inout} \
   CONFIG.PSU_MIO_34_POLARITY {Default} \
   CONFIG.PSU_MIO_35_DIRECTION {inout} \
   CONFIG.PSU_MIO_35_POLARITY {Default} \
   CONFIG.PSU_MIO_36_DIRECTION {inout} \
   CONFIG.PSU_MIO_36_POLARITY {Default} \
   CONFIG.PSU_MIO_37_DIRECTION {inout} \
   CONFIG.PSU_MIO_37_POLARITY {Default} \
   CONFIG.PSU_MIO_38_DIRECTION {inout} \
   CONFIG.PSU_MIO_38_POLARITY {Default} \
   CONFIG.PSU_MIO_39_DIRECTION {inout} \
   CONFIG.PSU_MIO_39_POLARITY {Default} \
   CONFIG.PSU_MIO_3_DIRECTION {inout} \
   CONFIG.PSU_MIO_3_POLARITY {Default} \
   CONFIG.PSU_MIO_40_DIRECTION {inout} \
   CONFIG.PSU_MIO_40_POLARITY {Default} \
   CONFIG.PSU_MIO_41_DIRECTION {inout} \
   CONFIG.PSU_MIO_41_POLARITY {Default} \
   CONFIG.PSU_MIO_42_DIRECTION {inout} \
   CONFIG.PSU_MIO_42_POLARITY {Default} \
   CONFIG.PSU_MIO_43_DIRECTION {inout} \
   CONFIG.PSU_MIO_43_POLARITY {Default} \
   CONFIG.PSU_MIO_44_DIRECTION {inout} \
   CONFIG.PSU_MIO_44_POLARITY {Default} \
   CONFIG.PSU_MIO_45_DIRECTION {inout} \
   CONFIG.PSU_MIO_45_POLARITY {Default} \
   CONFIG.PSU_MIO_46_DIRECTION {inout} \
   CONFIG.PSU_MIO_46_POLARITY {Default} \
   CONFIG.PSU_MIO_47_DIRECTION {inout} \
   CONFIG.PSU_MIO_47_POLARITY {Default} \
   CONFIG.PSU_MIO_48_DIRECTION {inout} \
   CONFIG.PSU_MIO_48_POLARITY {Default} \
   CONFIG.PSU_MIO_49_DIRECTION {inout} \
   CONFIG.PSU_MIO_49_POLARITY {Default} \
   CONFIG.PSU_MIO_4_DIRECTION {inout} \
   CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
   CONFIG.PSU_MIO_4_POLARITY {Default} \
   CONFIG.PSU_MIO_50_DIRECTION {inout} \
   CONFIG.PSU_MIO_50_POLARITY {Default} \
   CONFIG.PSU_MIO_51_DIRECTION {out} \
   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
   CONFIG.PSU_MIO_51_POLARITY {Default} \
   CONFIG.PSU_MIO_54_DIRECTION {in} \
   CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_54_POLARITY {Default} \
   CONFIG.PSU_MIO_54_SLEW {fast} \
   CONFIG.PSU_MIO_55_DIRECTION {out} \
   CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
   CONFIG.PSU_MIO_55_POLARITY {Default} \
   CONFIG.PSU_MIO_5_DIRECTION {out} \
   CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
   CONFIG.PSU_MIO_5_POLARITY {Default} \
   CONFIG.PSU_MIO_7_DIRECTION {out} \
   CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
   CONFIG.PSU_MIO_7_POLARITY {Default} \
   CONFIG.PSU_MIO_8_DIRECTION {inout} \
   CONFIG.PSU_MIO_8_POLARITY {Default} \
   CONFIG.PSU_MIO_9_DIRECTION {inout} \
   CONFIG.PSU_MIO_9_POLARITY {Default} \
   CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash##Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0####GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1###UART 0#UART 0######################} \
   CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out##n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out####gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#gpio1[31]#gpio1[32]#gpio1[33]#gpio1[34]#gpio1[35]#gpio1[36]#gpio1[37]#gpio1[38]#gpio1[39]#gpio1[40]#gpio1[41]#gpio1[42]#gpio1[43]#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out###rxd#txd######################} \
   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
   CONFIG.PSU__ACT_DDR_FREQ_MHZ {1200.000000} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {48} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {600.000000} \
   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1200} \
   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {48} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {63} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {10} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \
   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {42} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {60} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {266.666656} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {8} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {300.000000} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {32} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200.000000} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {200.000000} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {50.000000} \
   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {1} \
   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
   CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
   CONFIG.PSU__DDRC__CL {17} \
   CONFIG.PSU__DDRC__CWL {12} \
   CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \
   CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
   CONFIG.PSU__DDRC__ECC {Enabled} \
   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {ERR: 0  | 1} \
   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
   CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
   CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400P} \
   CONFIG.PSU__DDRC__T_FAW {30.0} \
   CONFIG.PSU__DDRC__T_RAS_MIN {32.0} \
   CONFIG.PSU__DDRC__T_RC {46.16} \
   CONFIG.PSU__DDRC__T_RCD {17} \
   CONFIG.PSU__DDRC__T_RP {17} \
   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \
   CONFIG.PSU__DLL__ISUSED {1} \
   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__GPIO_EMIO_WIDTH {3} \
   CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {3} \
   CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \
   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__I2C1__PERIPHERAL__IO {EMIO} \
   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;0|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0|LPD;USB3_0;FF9D0000;FF9DFFFF;0|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {50} \
   CONFIG.PSU__QSPI_COHERENCY {0} \
   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
   CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
   CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
   CONFIG.PSU__SD0_COHERENCY {0} \
   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {8Bit} \
   CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 22} \
   CONFIG.PSU__SD0__RESET__ENABLE {0} \
   CONFIG.PSU__SD0__SLOT_TYPE {eMMC} \
   CONFIG.PSU__SD1_COHERENCY {0} \
   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
   CONFIG.PSU__SD1__RESET__ENABLE {0} \
   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
   CONFIG.PSU__UART0__BAUD_RATE {115200} \
   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 54 .. 55} \
   CONFIG.PSU__USE__M_AXI_GP2 {0} \
   CONFIG.SUBPRESET1 {Custom} \
 ] $zynq_ultra_ps_e_0

  # Create port connections
  connect_bd_net -net Net [get_bd_ports EEPROM_SDA_0] [get_bd_pins util_ds_buf_1/IOBUF_IO_IO]
  connect_bd_net -net Net1 [get_bd_ports EEPROM_SCL] [get_bd_pins util_ds_buf_0/IOBUF_IO_IO]
  connect_bd_net -net Net4 [get_bd_ports BOARD_SCL_0] [get_bd_pins util_ds_buf_4/IOBUF_IO_IO]
  connect_bd_net -net Net5 [get_bd_ports BOARD_SDA_0] [get_bd_pins util_ds_buf_5/IOBUF_IO_IO]
  connect_bd_net -net sfp_det_i_0_1 [get_bd_ports sfp_det_i_0] [get_bd_pins wrc_board_diot_simple_0/sfp_det_i]
  connect_bd_net -net sfp_los_i_0_1 [get_bd_ports sfp_los_i_0] [get_bd_pins wrc_board_diot_simple_0/sfp_los_i]
  connect_bd_net -net sfp_rxn_i_0_1 [get_bd_ports sfp_rxn_i_0] [get_bd_pins wrc_board_diot_simple_0/sfp_rxn_i]
  connect_bd_net -net sfp_rxp_i_0_1 [get_bd_ports sfp_rxp_i_0] [get_bd_pins wrc_board_diot_simple_0/sfp_rxp_i]
  connect_bd_net -net uart_rxd_i_0_1 [get_bd_ports uart_rxd_i_0] [get_bd_pins wrc_board_diot_simple_0/uart_rxd_i]
  connect_bd_net -net util_ds_buf_0_IOBUF_IO_O [get_bd_pins util_ds_buf_0/IOBUF_IO_O] [get_bd_pins wrc_board_diot_simple_0/eeprom_scl_i]
  connect_bd_net -net util_ds_buf_1_IOBUF_IO_O [get_bd_pins util_ds_buf_1/IOBUF_IO_O] [get_bd_pins wrc_board_diot_simple_0/eeprom_sda_i]
  connect_bd_net -net util_ds_buf_4_IOBUF_IO_O [get_bd_pins util_ds_buf_4/IOBUF_IO_O] [get_bd_pins wrc_board_diot_simple_0/board_scl_i]
  connect_bd_net -net util_ds_buf_5_IOBUF_IO_O [get_bd_pins util_ds_buf_5/IOBUF_IO_O] [get_bd_pins wrc_board_diot_simple_0/board_sda_i]
  connect_bd_net -net wr_clk_helper_62_5m_n_i_0_1 [get_bd_ports wr_clk_helper_62_5m_n_i_0] [get_bd_pins wrc_board_diot_simple_0/wr_clk_helper_62_5m_n_i]
  connect_bd_net -net wr_clk_helper_62_5m_p_i_0_1 [get_bd_ports wr_clk_helper_62_5m_p_i_0] [get_bd_pins wrc_board_diot_simple_0/wr_clk_helper_62_5m_p_i]
  connect_bd_net -net wr_clk_main_62_5m_n_i_0_1 [get_bd_ports wr_clk_main_62_5m_n_i_0] [get_bd_pins wrc_board_diot_simple_0/wr_clk_main_62_5m_n_i]
  connect_bd_net -net wr_clk_main_62_5m_p_i_0_1 [get_bd_ports wr_clk_main_62_5m_p_i_0] [get_bd_pins wrc_board_diot_simple_0/wr_clk_main_62_5m_p_i]
  connect_bd_net -net wr_clk_sfp_125m_n_i_0_1 [get_bd_ports wr_clk_sfp_125m_n_i_0] [get_bd_pins wrc_board_diot_simple_0/wr_clk_sfp_125m_n_i]
  connect_bd_net -net wr_clk_sfp_125m_p_i_0_1 [get_bd_ports wr_clk_sfp_125m_p_i_0] [get_bd_pins wrc_board_diot_simple_0/wr_clk_sfp_125m_p_i]
  connect_bd_net -net wrc_board_diot_simple_0_board_scl_o [get_bd_pins util_ds_buf_4/IOBUF_IO_I] [get_bd_pins wrc_board_diot_simple_0/board_scl_o]
  connect_bd_net -net wrc_board_diot_simple_0_board_scl_t_o [get_bd_pins util_ds_buf_4/IOBUF_IO_T] [get_bd_pins wrc_board_diot_simple_0/board_scl_t_o]
  connect_bd_net -net wrc_board_diot_simple_0_board_sda_o [get_bd_pins util_ds_buf_5/IOBUF_IO_I] [get_bd_pins wrc_board_diot_simple_0/board_sda_o]
  connect_bd_net -net wrc_board_diot_simple_0_board_sda_t_o [get_bd_pins util_ds_buf_5/IOBUF_IO_T] [get_bd_pins wrc_board_diot_simple_0/board_sda_t_o]
  connect_bd_net -net wrc_board_diot_simple_0_eeprom_scl_o [get_bd_pins util_ds_buf_0/IOBUF_IO_I] [get_bd_pins util_ds_buf_0/IOBUF_IO_T] [get_bd_pins wrc_board_diot_simple_0/eeprom_scl_o]
  connect_bd_net -net wrc_board_diot_simple_0_eeprom_sda_o [get_bd_pins util_ds_buf_1/IOBUF_IO_I] [get_bd_pins util_ds_buf_1/IOBUF_IO_T] [get_bd_pins wrc_board_diot_simple_0/eeprom_sda_o]
  connect_bd_net -net wrc_board_diot_simple_0_led_act_o [get_bd_ports led_act_o_0] [get_bd_pins wrc_board_diot_simple_0/led_act_o]
  connect_bd_net -net wrc_board_diot_simple_0_led_link_o [get_bd_ports led_link_o_0] [get_bd_pins wrc_board_diot_simple_0/led_link_o]
  connect_bd_net -net wrc_board_diot_simple_0_pll20dac_cs_n_o [get_bd_ports pll20dac_cs_n_o_0] [get_bd_pins wrc_board_diot_simple_0/pll20dac_cs_n_o]
  connect_bd_net -net wrc_board_diot_simple_0_pll25dac_cs_n_o [get_bd_ports pll25dac_cs_n_o_0] [get_bd_pins wrc_board_diot_simple_0/pll25dac_cs_n_o]
  connect_bd_net -net wrc_board_diot_simple_0_plldac_din_o [get_bd_ports plldac_din_o_0] [get_bd_pins wrc_board_diot_simple_0/plldac_din_o]
  connect_bd_net -net wrc_board_diot_simple_0_plldac_sclk_o [get_bd_ports plldac_sclk_o_0] [get_bd_pins wrc_board_diot_simple_0/plldac_sclk_o]
  connect_bd_net -net wrc_board_diot_simple_0_pps_led_o [get_bd_ports pps_led_o_0] [get_bd_pins wrc_board_diot_simple_0/pps_led_o]
  connect_bd_net -net wrc_board_diot_simple_0_pps_p_o [get_bd_ports pps_p_o_0] [get_bd_pins wrc_board_diot_simple_0/pps_p_o]
  connect_bd_net -net wrc_board_diot_simple_0_ps_scl_o [get_bd_pins wrc_board_diot_simple_0/ps_scl_o] [get_bd_pins zynq_ultra_ps_e_0/emio_i2c1_scl_i]
  connect_bd_net -net wrc_board_diot_simple_0_ps_sda_o [get_bd_pins wrc_board_diot_simple_0/ps_sda_o] [get_bd_pins zynq_ultra_ps_e_0/emio_i2c1_sda_i]
  connect_bd_net -net wrc_board_diot_simple_0_sfp_txn_o [get_bd_ports sfp_txn_o_0] [get_bd_pins wrc_board_diot_simple_0/sfp_txn_o]
  connect_bd_net -net wrc_board_diot_simple_0_sfp_txp_o [get_bd_ports sfp_txp_o_0] [get_bd_pins wrc_board_diot_simple_0/sfp_txp_o]
  connect_bd_net -net wrc_board_diot_simple_0_uart_txd_o [get_bd_ports uart_txd_o_0] [get_bd_pins wrc_board_diot_simple_0/uart_txd_o]
  connect_bd_net -net zynq_ultra_ps_e_0_emio_gpio_o [get_bd_pins wrc_board_diot_simple_0/emio_i] [get_bd_pins zynq_ultra_ps_e_0/emio_gpio_i] [get_bd_pins zynq_ultra_ps_e_0/emio_gpio_o]
  connect_bd_net -net zynq_ultra_ps_e_0_emio_i2c1_scl_o [get_bd_pins wrc_board_diot_simple_0/ps_scl_i] [get_bd_pins zynq_ultra_ps_e_0/emio_i2c1_scl_o]
  connect_bd_net -net zynq_ultra_ps_e_0_emio_i2c1_scl_t [get_bd_pins wrc_board_diot_simple_0/ps_scl_t_i] [get_bd_pins zynq_ultra_ps_e_0/emio_i2c1_scl_t]
  connect_bd_net -net zynq_ultra_ps_e_0_emio_i2c1_sda_o [get_bd_pins wrc_board_diot_simple_0/ps_sda_i] [get_bd_pins zynq_ultra_ps_e_0/emio_i2c1_sda_o]
  connect_bd_net -net zynq_ultra_ps_e_0_emio_i2c1_sda_t [get_bd_pins wrc_board_diot_simple_0/ps_sda_t_i] [get_bd_pins zynq_ultra_ps_e_0/emio_i2c1_sda_t]
  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins wrc_board_diot_simple_0/areset_n_i] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]

  # Create address segments

  # Perform GUI Layout
  regenerate_bd_layout -layout_string {
   "ActiveEmotionalView":"Default View",
   "Default View_ScaleFactor":"0.536585",
   "Default View_TopLeft":"-255,-41",
   "ExpandedHierarchyInLayout":"",
   "guistr":"# # String gsaved with Nlview 7.0.21  2019-05-29 bk=1.5064 VDI=41 GEI=36 GUI=JA:9.0 TLS
#  -string -flagsOSRD
preplace port wr_clk_helper_62_5m_p_i_0 -pg 1 -lvl 0 -x -10 -y 370 -defaultsOSRD
preplace port wr_clk_helper_62_5m_n_i_0 -pg 1 -lvl 0 -x -10 -y 390 -defaultsOSRD
preplace port led_act_o_0 -pg 1 -lvl 4 -x 1390 -y 590 -defaultsOSRD
preplace port led_link_o_0 -pg 1 -lvl 4 -x 1390 -y 610 -defaultsOSRD
preplace port pll20dac_cs_n_o_0 -pg 1 -lvl 4 -x 1390 -y 350 -defaultsOSRD
preplace port pll25dac_cs_n_o_0 -pg 1 -lvl 4 -x 1390 -y 330 -defaultsOSRD
preplace port plldac_din_o_0 -pg 1 -lvl 4 -x 1390 -y 290 -defaultsOSRD
preplace port plldac_sclk_o_0 -pg 1 -lvl 4 -x 1390 -y 310 -defaultsOSRD
preplace port pps_led_o_0 -pg 1 -lvl 4 -x 1390 -y 670 -defaultsOSRD
preplace port pps_p_o_0 -pg 1 -lvl 4 -x 1390 -y 650 -defaultsOSRD
preplace port sfp_los_i_0 -pg 1 -lvl 0 -x -10 -y 610 -defaultsOSRD
preplace port sfp_rxn_i_0 -pg 1 -lvl 0 -x -10 -y 590 -defaultsOSRD
preplace port sfp_rxp_i_0 -pg 1 -lvl 0 -x -10 -y 570 -defaultsOSRD
preplace port sfp_txn_o_0 -pg 1 -lvl 4 -x 1390 -y 630 -defaultsOSRD
preplace port sfp_txp_o_0 -pg 1 -lvl 4 -x 1390 -y 690 -defaultsOSRD
preplace port uart_rxd_i_0 -pg 1 -lvl 0 -x -10 -y 650 -defaultsOSRD
preplace port uart_txd_o_0 -pg 1 -lvl 4 -x 1390 -y 710 -defaultsOSRD
preplace port wr_clk_main_62_5m_n_i_0 -pg 1 -lvl 0 -x -10 -y 430 -defaultsOSRD
preplace port wr_clk_main_62_5m_p_i_0 -pg 1 -lvl 0 -x -10 -y 410 -defaultsOSRD
preplace port wr_clk_sfp_125m_n_i_0 -pg 1 -lvl 0 -x -10 -y 470 -defaultsOSRD
preplace port wr_clk_sfp_125m_p_i_0 -pg 1 -lvl 0 -x -10 -y 450 -defaultsOSRD
preplace port sfp_det_i_0 -pg 1 -lvl 0 -x -10 -y 630 -defaultsOSRD
preplace portBus EEPROM_SDA_0 -pg 1 -lvl 4 -x 1390 -y 230 -defaultsOSRD
preplace portBus EEPROM_SCL -pg 1 -lvl 4 -x 1390 -y 90 -defaultsOSRD
preplace portBus BOARD_SCL_0 -pg 1 -lvl 4 -x 1390 -y 550 -defaultsOSRD
preplace portBus BOARD_SDA_0 -pg 1 -lvl 4 -x 1390 -y 430 -defaultsOSRD
preplace inst zynq_ultra_ps_e_0 -pg 1 -lvl 1 -x 270 -y 870 -defaultsOSRD
preplace inst util_ds_buf_0 -pg 1 -lvl 3 -x 1190 -y 80 -defaultsOSRD
preplace inst util_ds_buf_1 -pg 1 -lvl 3 -x 1190 -y 220 -defaultsOSRD
preplace inst util_ds_buf_4 -pg 1 -lvl 3 -x 1190 -y 540 -defaultsOSRD
preplace inst util_ds_buf_5 -pg 1 -lvl 3 -x 1190 -y 420 -defaultsOSRD
preplace inst wrc_board_diot_simple_0 -pg 1 -lvl 2 -x 780 -y 530 -defaultsOSRD
preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 1 1 540 330n
preplace netloc wr_clk_helper_62_5m_p_i_0_1 1 0 2 NJ 370 NJ
preplace netloc wr_clk_helper_62_5m_n_i_0_1 1 0 2 NJ 390 NJ
preplace netloc wrc_board_diot_simple_0_eeprom_scl_o 1 2 1 980 70n
preplace netloc util_ds_buf_0_IOBUF_IO_O 1 1 3 560 10 NJ 10 1340
preplace netloc wrc_board_diot_simple_0_eeprom_sda_o 1 2 1 990 210n
preplace netloc util_ds_buf_1_IOBUF_IO_O 1 1 3 580 150 NJ 150 1340
preplace netloc Net 1 3 1 NJ 230
preplace netloc Net1 1 3 1 NJ 90
preplace netloc wrc_board_diot_simple_0_led_act_o 1 2 2 NJ 610 1350J
preplace netloc wrc_board_diot_simple_0_led_link_o 1 2 2 1010J 620 1360J
preplace netloc wrc_board_diot_simple_0_pll20dac_cs_n_o 1 2 2 1020J 350 NJ
preplace netloc wrc_board_diot_simple_0_pll25dac_cs_n_o 1 2 2 1000J 330 NJ
preplace netloc wrc_board_diot_simple_0_plldac_din_o 1 2 2 1010J 340 1360J
preplace netloc wrc_board_diot_simple_0_plldac_sclk_o 1 2 2 970J 310 NJ
preplace netloc wrc_board_diot_simple_0_pps_led_o 1 2 2 NJ 670 NJ
preplace netloc wrc_board_diot_simple_0_pps_p_o 1 2 2 NJ 650 NJ
preplace netloc sfp_los_i_0_1 1 0 2 NJ 610 NJ
preplace netloc sfp_rxn_i_0_1 1 0 2 NJ 590 NJ
preplace netloc sfp_rxp_i_0_1 1 0 2 NJ 570 NJ
preplace netloc wrc_board_diot_simple_0_sfp_txn_o 1 2 2 1030J 630 NJ
preplace netloc wrc_board_diot_simple_0_sfp_txp_o 1 2 2 990J 690 NJ
preplace netloc uart_rxd_i_0_1 1 0 2 NJ 650 NJ
preplace netloc wrc_board_diot_simple_0_uart_txd_o 1 2 2 970J 640 1350J
preplace netloc wr_clk_main_62_5m_n_i_0_1 1 0 2 NJ 430 NJ
preplace netloc wr_clk_main_62_5m_p_i_0_1 1 0 2 NJ 410 NJ
preplace netloc wr_clk_sfp_125m_n_i_0_1 1 0 2 NJ 470 NJ
preplace netloc wr_clk_sfp_125m_p_i_0_1 1 0 2 NJ 450 NJ
preplace netloc Net4 1 3 1 NJ 550
preplace netloc Net5 1 3 1 NJ 430
preplace netloc wrc_board_diot_simple_0_board_sda_t_o 1 2 1 1030 410n
preplace netloc wrc_board_diot_simple_0_board_sda_o 1 2 1 1040 430n
preplace netloc util_ds_buf_5_IOBUF_IO_O 1 1 3 570 270 1020J 290 1340
preplace netloc wrc_board_diot_simple_0_board_scl_t_o 1 2 1 1030 510n
preplace netloc wrc_board_diot_simple_0_board_scl_o 1 2 1 1010 530n
preplace netloc util_ds_buf_4_IOBUF_IO_O 1 1 3 580 790 NJ 790 1340
preplace netloc zynq_ultra_ps_e_0_emio_i2c1_scl_o 1 1 1 530 670n
preplace netloc zynq_ultra_ps_e_0_emio_i2c1_scl_t 1 1 1 550 690n
preplace netloc zynq_ultra_ps_e_0_emio_i2c1_sda_o 1 1 1 560 710n
preplace netloc zynq_ultra_ps_e_0_emio_i2c1_sda_t 1 1 1 570 730n
preplace netloc wrc_board_diot_simple_0_ps_scl_o 1 1 2 NJ 840 980
preplace netloc wrc_board_diot_simple_0_ps_sda_o 1 1 2 NJ 900 970
preplace netloc zynq_ultra_ps_e_0_emio_gpio_o 1 1 1 520 350n
preplace netloc sfp_det_i_0_1 1 0 2 NJ 630 NJ
levelinfo -pg 1 -10 270 780 1190 1390
pagesize -pg 1 -db -bbox -sgen -260 0 1590 1050
"
}

  # Restore current instance
  current_bd_instance $oldCurInst

  validate_bd_design
  save_bd_design
  close_bd_design $design_name 
}
# End of cr_bd_design_1()
cr_bd_design_1 ""
set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ] 
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ] 

# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
    create_run -name synth_1 -part xczu7cg-ffvf1517-1-e -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
} else {
  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
  set_property flow "Vivado Synthesis 2019" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Synthesis Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'synth_1_synth_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
}
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
if { $obj != "" } {

}
set obj [get_runs synth_1]
set_property -name "needs_refresh" -value "1" -objects $obj
set_property -name "part" -value "xczu7cg-ffvf1517-1-e" -objects $obj
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj

# set the current synth run
current_run -synthesis [get_runs synth_1]

# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
    create_run -name impl_1 -part xczu7cg-ffvf1517-1-e -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
} else {
  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
  set_property flow "Vivado Implementation 2019" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Implementation Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_1_opt_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
if { $obj != "" } {

}
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_1_place_report_io_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
if { $obj != "" } {

}
# Create 'impl_1_place_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
if { $obj != "" } {

}
# Create 'impl_1_place_report_control_sets_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
if { $obj != "" } {
set_property -name "options.verbose" -value "1" -objects $obj

}
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj

}
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj

}
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_1_route_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_methodology_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_power_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_route_status_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
if { $obj != "" } {
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
if { $obj != "" } {

}
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
if { $obj != "" } {
set_property -name "options.warn_on_violation" -value "1" -objects $obj

}
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.warn_on_violation" -value "1" -objects $obj

}
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
if { $obj != "" } {
set_property -name "options.warn_on_violation" -value "1" -objects $obj

}
set obj [get_runs impl_1]
set_property -name "needs_refresh" -value "1" -objects $obj
set_property -name "part" -value "xczu7cg-ffvf1517-1-e" -objects $obj
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj

# set the current impl run
current_run -implementation [get_runs impl_1]

puts "INFO: Project created:${_xil_proj_name_}"
# Create 'drc_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
create_dashboard_gadget -name {drc_1} -type drc
}
set obj [get_dashboard_gadgets [ list "drc_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj

# Create 'methodology_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
create_dashboard_gadget -name {methodology_1} -type methodology
}
set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj

# Create 'power_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
create_dashboard_gadget -name {power_1} -type power
}
set obj [get_dashboard_gadgets [ list "power_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj

# Create 'timing_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
create_dashboard_gadget -name {timing_1} -type timing
}
set obj [get_dashboard_gadgets [ list "timing_1" ] ]
set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj

# Create 'utilization_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
create_dashboard_gadget -name {utilization_1} -type utilization
}
set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
set_property -name "run.step" -value "synth_design" -objects $obj
set_property -name "run.type" -value "synthesis" -objects $obj

# Create 'utilization_2' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
create_dashboard_gadget -name {utilization_2} -type utilization
}
set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj

move_dashboard_gadget -name {utilization_1} -row 0 -col 0
move_dashboard_gadget -name {power_1} -row 1 -col 0
move_dashboard_gadget -name {drc_1} -row 2 -col 0
move_dashboard_gadget -name {timing_1} -row 0 -col 1
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
move_dashboard_gadget -name {methodology_1} -row 2 -col 1
