/*
  Register definitions for slave core: Mock Turtle CPU Control/Status registers block

  * File           : wrc_cpu_csr.h
  * Author         : auto-generated by wbgen2 from wrc_cpu_csr.wb
  * Created        : Mon Mar 28 16:12:19 2022
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_cpu_csr.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_WRC_CPU_CSR_WB
#define __WBGEN2_REGDEFS_WRC_CPU_CSR_WB

#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Core Reset Register */

/* definitions for register: Core Upload Address Register */

/* definitions for field: Address to access in selected core's local memory. in reg: Core Upload Address Register */
#define WRC_CPU_CSR_UADDR_ADDR_MASK           WBGEN2_GEN_MASK(0, 20)
#define WRC_CPU_CSR_UADDR_ADDR_SHIFT          0
#define WRC_CPU_CSR_UADDR_ADDR_W(value)       WBGEN2_GEN_WRITE(value, 0, 20)
#define WRC_CPU_CSR_UADDR_ADDR_R(reg)         WBGEN2_GEN_READ(reg, 0, 20)

/* definitions for register: Core Upload Data Register */

/* definitions for register: Debug Interface Status Register */

/* definitions for register: Debug Interface Force Register */

/* definitions for register: Debug Interface Instruction Ready Register */

/* definitions for register: Debug Interface Core[0] Instruction Register */

/* definitions for register: Debug Interface Core[0] Mailbox Data Register */
/* [0x0]: REG Core Reset Register */
#define WRC_CPU_CSR_REG_RESET 0x00000000
/* [0x4]: REG Core Upload Address Register */
#define WRC_CPU_CSR_REG_UADDR 0x00000004
/* [0x8]: REG Core Upload Data Register */
#define WRC_CPU_CSR_REG_UDATA 0x00000008
/* [0x80]: REG Debug Interface Status Register */
#define WRC_CPU_CSR_REG_DBG_STATUS 0x00000080
/* [0x84]: REG Debug Interface Force Register */
#define WRC_CPU_CSR_REG_DBG_FORCE 0x00000084
/* [0x88]: REG Debug Interface Instruction Ready Register */
#define WRC_CPU_CSR_REG_DBG_INSN_READY 0x00000088
/* [0x8c]: REG Debug Interface Core[0] Instruction Register */
#define WRC_CPU_CSR_REG_DBG_CORE0_INSN 0x0000008c
/* [0x90]: REG Debug Interface Core[0] Mailbox Data Register */
#define WRC_CPU_CSR_REG_DBG_CORE0_MBX 0x00000090
#endif
