/*
  Register definitions for slave core: WR RF transmission control

  * File           : wr_rf_frame_transceiver_regs.h
  * Author         : auto-generated by wbgen2 from RF_wb.wb
  * Created        : Thu Mar 26 17:24:03 2020
  * Version        : 0x00000001
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE RF_wb.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_RF_WB_WB
#define __WBGEN2_REGDEFS_RF_WB_WB

#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif

/* version definition */
#define WBGEN2_RF_VERSION 0x00000001


/* definitions for register: Version register */

/* definitions for field: Version identifier in reg: Version register */
#define RF_VER_ID_MASK                        WBGEN2_GEN_MASK(0, 32)
#define RF_VER_ID_SHIFT                       0
#define RF_VER_ID_W(value)                    WBGEN2_GEN_WRITE(value, 0, 32)
#define RF_VER_ID_R(reg)                      WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: Status and ctontrol register */

/* definitions for field: Transmit single frame in reg: Status and ctontrol register */
#define RF_SCR_TX_SINGLE                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Debug mode in reg: Status and ctontrol register */
#define RF_SCR_TX_DBG_MASK                    WBGEN2_GEN_MASK(1, 2)
#define RF_SCR_TX_DBG_SHIFT                   1
#define RF_SCR_TX_DBG_W(value)                WBGEN2_GEN_WRITE(value, 1, 2)
#define RF_SCR_TX_DBG_R(reg)                  WBGEN2_GEN_READ(reg, 1, 2)

/* definitions for field: Debug Frame type in reg: Status and ctontrol register */
#define RF_SCR_TX_DBG_FTYPE_MASK              WBGEN2_GEN_MASK(4, 4)
#define RF_SCR_TX_DBG_FTYPE_SHIFT             4
#define RF_SCR_TX_DBG_FTYPE_W(value)          WBGEN2_GEN_WRITE(value, 4, 4)
#define RF_SCR_TX_DBG_FTYPE_R(reg)            WBGEN2_GEN_READ(reg, 4, 4)

/* definitions for field: Invert RX valid polarity in reg: Status and ctontrol register */
#define RF_SCR_RX_VALID_POL_INV               WBGEN2_GEN_MASK(8, 1)

/* definitions for field: TX override default config in reg: Status and ctontrol register */
#define RF_SCR_TX_OR_CONFIG                   WBGEN2_GEN_MASK(9, 1)

/* definitions for field: RX override default config in reg: Status and ctontrol register */
#define RF_SCR_RX_OR_CONFIG                   WBGEN2_GEN_MASK(10, 1)

/* definitions for field: Dummy in reg: Status and ctontrol register */
#define RF_SCR_DUMMY_MASK                     WBGEN2_GEN_MASK(16, 16)
#define RF_SCR_DUMMY_SHIFT                    16
#define RF_SCR_DUMMY_W(value)                 WBGEN2_GEN_WRITE(value, 16, 16)
#define RF_SCR_DUMMY_R(reg)                   WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: Transmission period */

/* definitions for field: Period in clock cylces (16ns). When the value is not zero, frames are sent with that period.  in reg: Transmission period */
#define RF_TX_PERIOD_VALUE_MASK               WBGEN2_GEN_MASK(0, 32)
#define RF_TX_PERIOD_VALUE_SHIFT              0
#define RF_TX_PERIOD_VALUE_W(value)           WBGEN2_GEN_WRITE(value, 0, 32)
#define RF_TX_PERIOD_VALUE_R(reg)             WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: Rx output data valid delay and period */

/* definitions for field: Output data valid period in reg: Rx output data valid delay and period */
#define RF_RX_OUT_DATA_TIME_VALID_MASK        WBGEN2_GEN_MASK(0, 16)
#define RF_RX_OUT_DATA_TIME_VALID_SHIFT       0
#define RF_RX_OUT_DATA_TIME_VALID_W(value)    WBGEN2_GEN_WRITE(value, 0, 16)
#define RF_RX_OUT_DATA_TIME_VALID_R(reg)      WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Output data delay in reg: Rx output data valid delay and period */
#define RF_RX_OUT_DATA_TIME_DELAY_MASK        WBGEN2_GEN_MASK(16, 16)
#define RF_RX_OUT_DATA_TIME_DELAY_SHIFT       16
#define RF_RX_OUT_DATA_TIME_DELAY_W(value)    WBGEN2_GEN_WRITE(value, 16, 16)
#define RF_RX_OUT_DATA_TIME_DELAY_R(reg)      WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: SimRFval: control subcycles */

/* definitions for field: Cycle Length in reg: SimRFval: control subcycles */
#define RF_SIMRF_CTRL_CLEN_MASK               WBGEN2_GEN_MASK(0, 4)
#define RF_SIMRF_CTRL_CLEN_SHIFT              0
#define RF_SIMRF_CTRL_CLEN_W(value)           WBGEN2_GEN_WRITE(value, 0, 4)
#define RF_SIMRF_CTRL_CLEN_R(reg)             WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for field: Sub-cycle ID in reg: SimRFval: control subcycles */
#define RF_SIMRF_CTRL_SCID_MASK               WBGEN2_GEN_MASK(4, 4)
#define RF_SIMRF_CTRL_SCID_SHIFT              4
#define RF_SIMRF_CTRL_SCID_W(value)           WBGEN2_GEN_WRITE(value, 4, 4)
#define RF_SIMRF_CTRL_SCID_R(reg)             WBGEN2_GEN_READ(reg, 4, 4)

/* definitions for field: Cycle maximum length in reg: SimRFval: control subcycles */
#define RF_SIMRF_CTRL_CMAXLEN_MASK            WBGEN2_GEN_MASK(8, 4)
#define RF_SIMRF_CTRL_CMAXLEN_SHIFT           8
#define RF_SIMRF_CTRL_CMAXLEN_W(value)        WBGEN2_GEN_WRITE(value, 8, 4)
#define RF_SIMRF_CTRL_CMAXLEN_R(reg)          WBGEN2_GEN_READ(reg, 8, 4)

/* definitions for register: SimRFval: Sub-cycle lenght */

/* definitions for field: Lenght in sent frames, i.e. the  in reg: SimRFval: Sub-cycle lenght */
#define RF_RFSIM_SCYC_LEN_VAL_MASK            WBGEN2_GEN_MASK(0, 32)
#define RF_RFSIM_SCYC_LEN_VAL_SHIFT           0
#define RF_RFSIM_SCYC_LEN_VAL_W(value)        WBGEN2_GEN_WRITE(value, 0, 32)
#define RF_RFSIM_SCYC_LEN_VAL_R(reg)          WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: SimRFval: Sub-cycle increment */

/* definitions for field: Signed value that is added to the RFvalue each time RF frame is transmitted. in reg: SimRFval: Sub-cycle increment */
#define RF_RFSIM_SCYC_INC_VAL_MASK            WBGEN2_GEN_MASK(0, 16)
#define RF_RFSIM_SCYC_INC_VAL_SHIFT           0
#define RF_RFSIM_SCYC_INC_VAL_W(value)        WBGEN2_GEN_WRITE(value, 0, 16)
#define RF_RFSIM_SCYC_INC_VAL_R(reg)          WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for register: DBG RX RFm or RFs value */

/* definitions for register: DBG TX RFm or RFs value, depending which frame */
/* [0x0]: REG Version register */
#define RF_REG_VER 0x00000000
/* [0x4]: REG Status and ctontrol register */
#define RF_REG_SCR 0x00000004
/* [0x8]: REG Transmission period */
#define RF_REG_TX_PERIOD 0x00000008
/* [0xc]: REG Rx output data valid delay and period */
#define RF_REG_RX_OUT_DATA_TIME 0x0000000c
/* [0x10]: REG SimRFval: control subcycles */
#define RF_REG_SIMRF_CTRL 0x00000010
/* [0x14]: REG SimRFval: Sub-cycle lenght */
#define RF_REG_RFSIM_SCYC_LEN 0x00000014
/* [0x18]: REG SimRFval: Sub-cycle increment */
#define RF_REG_RFSIM_SCYC_INC 0x00000018
/* [0x1c]: REG DBG RX RFm or RFs value */
#define RF_REG_DBG_RX_RFM_OR_RFS 0x0000001c
/* [0x20]: REG DBG TX RFm or RFs value, depending which frame */
#define RF_REG_DBG_TX_RFM_OR_RFS 0x00000020
#endif
