/*
  Register definitions for slave core: Clock Frequency Monitor

  * File           : wb_clock_monitor.h
  * Author         : auto-generated by wbgen2 from clock_monitor_wb.wb
  * Created        : Mon Jun 17 18:28:42 2019
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE clock_monitor_wb.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_CLOCK_MONITOR_WB_WB
#define __WBGEN2_REGDEFS_CLOCK_MONITOR_WB_WB

#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Control Register */

/* definitions for field: Reset counters in reg: Control Register */
#define CM_CR_CNT_RST                         WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Prescaler in reg: Control Register */
#define CM_CR_PRESC_MASK                      WBGEN2_GEN_MASK(1, 8)
#define CM_CR_PRESC_SHIFT                     1
#define CM_CR_PRESC_W(value)                  WBGEN2_GEN_WRITE(value, 1, 8)
#define CM_CR_PRESC_R(reg)                    WBGEN2_GEN_READ(reg, 1, 8)

/* definitions for field: Reference Select in reg: Control Register */
#define CM_CR_REFSEL_MASK                     WBGEN2_GEN_MASK(9, 4)
#define CM_CR_REFSEL_SHIFT                    9
#define CM_CR_REFSEL_W(value)                 WBGEN2_GEN_WRITE(value, 9, 4)
#define CM_CR_REFSEL_R(reg)                   WBGEN2_GEN_READ(reg, 9, 4)

/* definitions for register: Reference Divider Register */

/* definitions for field: Reference Division Ratio in reg: Reference Divider Register */
#define CM_REFDR_REFDR_MASK                   WBGEN2_GEN_MASK(0, 32)
#define CM_REFDR_REFDR_SHIFT                  0
#define CM_REFDR_REFDR_W(value)               WBGEN2_GEN_WRITE(value, 0, 32)
#define CM_REFDR_REFDR_R(reg)                 WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: Counter Select Register */

/* definitions for field: Counter Select in reg: Counter Select Register */
#define CM_CNT_SEL_SEL_MASK                   WBGEN2_GEN_MASK(0, 4)
#define CM_CNT_SEL_SEL_SHIFT                  0
#define CM_CNT_SEL_SEL_W(value)               WBGEN2_GEN_WRITE(value, 0, 4)
#define CM_CNT_SEL_SEL_R(reg)                 WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for register: Counter Value Register */

/* definitions for field: Counter Value in reg: Counter Value Register */
#define CM_CNT_VAL_VALUE_MASK                 WBGEN2_GEN_MASK(0, 31)
#define CM_CNT_VAL_VALUE_SHIFT                0
#define CM_CNT_VAL_VALUE_W(value)             WBGEN2_GEN_WRITE(value, 0, 31)
#define CM_CNT_VAL_VALUE_R(reg)               WBGEN2_GEN_READ(reg, 0, 31)

/* definitions for field: Counter Value Valid/Clear in reg: Counter Value Register */
#define CM_CNT_VAL_VALID                      WBGEN2_GEN_MASK(31, 1)
/* [0x0]: REG Control Register */
#define CM_REG_CR 0x00000000
/* [0x4]: REG Reference Divider Register */
#define CM_REG_REFDR 0x00000004
/* [0x8]: REG Counter Select Register */
#define CM_REG_CNT_SEL 0x00000008
/* [0xc]: REG Counter Value Register */
#define CM_REG_CNT_VAL 0x0000000c
#endif
