The AsyncArt Project is comprised by a set of Open-Source HDL libraries targeted to the efficient implementation of clockless/asynchronous circuits over Commercial-Off-The-Shelf devices & technologies.
It's worthy to note that, more than a standard library, the core of the AsyncArt project is a collection of very simple reference design examples that contain useful tricks and methodologies that can be easily applied to more complex projects.
Even the fact that the introduced design approach has also been tested in custom CMOS IC designs, FPGA technology is key to the AsyncArt project as an affordable and flexible tool for research & educational use and low-volume commercial production.
Asynchronous macro-modules were a Pain to Build but a Joy to Use
Wesley A. Clark
Asynchronous logic design may be a very hard subject. In order to fully understand the power of this kind of design and its potential advantages over the traditional synchronous paradigm, relatively strong theoretical foundations and practical skills should be previously acquired.
There are plenty of educative material online about asynchronous logic design, but there is a little gem than shines over the rest of available books, papers or tutorials. This gem is the book Principles of asynchronous circuit design - A systems perspective, published in 2001 by Jens Sparsoe & Steve Furber (more precisely, the chapters 1-8 by Sparsoe, freely available for non-commercial educational use since 2006).
For those designers used to asynchronous design, the subtle design tricks & details present in the AsyncArt reference designs will be clear enough after reading the next paper (the content is also available in the AsyncArt webpage):
Is important to note that the concrete approach introduced in this paper only covers a limited set of the presented reference designs, but the core signaling mechanism is shared in one way or another by all of them.
Follow this link to access the Reference Design Catalog
As noted before, more than a standard HDL library, the AsyncArt project contains a collection of demonstrative reference designs that contains tricks and blocks than can be easily reused.
In order to make easier the use of this techniques for educative purposes, the released reference designs has been standarized by porting them to a free to use project development environment.
By date of 2012/12/27, the development environment is comprised by:
- Operative System: Scientific Linux 6, a Linux release put together by Fermilab, CERN, and various other labs and universities around the world. Its primary purpose is to reduce duplicated effort of the labs, and to have a common install base for the various experimenters. The base SL distribution is basically Enterprise Linux, recompiled from source. The main goal for the base distribution is to have everything compatible with Enterprise, with only a few minor additions or changes.
- Integrated Design Environment: Xilinx ISE Webpack 14, the industry´s only FREE, fully featured front-to-back FPGA design solution for Linux, Windows XP, and Windows 7. ISE WebPACK is the ideal downloadable solution for FPGA and CPLD design offering HDL synthesis and simulation, implementation, device fitting, and JTAG programming.
The AsyncArt project deriverables are then compressed full Xilinx ISE projects, all of them consisting in two fundamental blocks:
- TOP-Level Schematic: when dealing with asynchronous design, being conscious of the dynamics and geometry of critical signal paths is a key issue. By this reason, the AsyncArt reference designs are released as visually descriptive schematics files.
Design tip: hierachy is critical when synthesizing an asynchronous design. For a successful synthesis, Keep Hierachy property should be enabled.
- HDL TestBench: as a quick-start to real work, with every schematic is attached a testbench ready to be simulated. This testbench contains information related to the input operation & purpose and the output that should be observed.
Design tip: Real world delays are the big deal with asynchronous logic. For a successful simulation, Post Place & Route models should be used.
NOTE: A single design deliverable may contain more than one schematic/testbench pair
The licensing policy of the AsyncArt project is quite simple and can be resumed in the nexts facts:
- You are granted to use the HDL code provided as a IP-Core library in any design, and by doing this you are not forced to disclose the other IP-Cores involved in the system.
- If you change or improve the HDL code in any way, you must share your modifications with the open-source design community.
To clarify the licensing terms, we have chosen the LGPLv2.0 license, the most optimal available one, in order to fullfill the previous facts in a satisfactory way.