Description

The goal of the CernFIP project is to provide a radiation tolerant FPGA-based replacement for Alstom 's WorldFIP agent, the MicroFIP chip.
This replacement is called nanoFIP.


The is a rad-tol FPGA that acts as a client node in the communication over the WorldFIP fieldbus.
It is housed in a Microsemi ProASIC3, A3P400, 208 PQFP FPGA.
The nanoFIP implements a minimal subset of the WorldFIP services and is designed to be radiation tolerant by using different SEU mitigation techniques such as TMR and fail-safe state machines.
It is used in conjunction with a FielDrive driver chip and FieldTR insulating transformer, both available from the company Alstom.


Project Material

nanoFIP functional specification
WorldFIP standards
WorldFIP insourcing work packages
nanoFIP presentations, papers and meetings' minutes
nanoFIP functionality tests, EMC tests and radiation tests
nanoFIP VHDL modules, hints n' tips guide, pinout list and pdb file

Project Status

Date Event
16-02-2009 Start of insourcing project
13-10-2010 First code working on nanoFIP test board
15-04-2011 Preliminary radiation tests performed on nanoFIP design
17-05-2011 Stable design available for use in critical applications
08-2011 Finalization of project's extension with JTAG Master
10-2011 nanoFIP-FielDrive-FieldTR EMC tests
11-2011 nanoFIP final code review; code frozen
12-2011 Large scale radiation tests performed on nanoFIP design
01-2012 Ongoing users' developments!-)
05-2012 Preparing very large order for preprogrammed nanoFIP FPGAs

nanoFIP users

Equipment Designer Status
CERN Radiation Monitoring Paul Peronnard March 2012: prototype working
FIPDIAG HLP company May 2012: prototype working
CERN Power Converter Controls Benjamin Todd March 2012: start designing
CERN Cryogenic Controls Juan Casas Cubillos within 2012: start designing
CERN Quench Protection Systems Jens Steckert June 2011: prototype board EDA-02138 never powered (May 2012).
May use nanoFIP as IP in 2014.
Train renovation April 2012: evaluating

Contacts

Erik van der Bij (Project manager) o Eva Gousiou (Lead engineer) o Pablo Alvarez (Development engineer) o Gonzalo Penacoba (VHDL test bench) o Julien Palluel (WorldFIP testbed software)



E.Gousiou, E.Van der Bij, May 2012