Here are our current LTSpice models for the front end. If you have any comments or observations please share them!
The model consists of three main blocks:
Transimpedence front end amplifier
Two stage signal amplifier + Pulse shaping network
The main schematic (developed in EagleCad) is presented for design review. If you have comments, questions or suggestions please share them with us! Once we've finished on the schematic we'll move to finalise the layout, and we might have another review if necessary. The BOM is also attached.
Here is our latest front end schematic! Comments welcome. We're currently testing it with some Advansid SiPM's as a signal source.
Summary of bugs and changes:
Voltage reference IC U4 changes to NCP51460SN33T1G - a 3.3V SOT23 voltage reference, RS part 719-2642
Nand gate IC1 changes to AND gate SN74AHC1G08D8VR, RS part 526-436
R21 changes to 200k, new value of resistor.
R22 changes to 10k, an existing value