Overview

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

  • Status: Beta

Latest news


First prototype of the core available

The prototype of the DDR3 controller is based on the SP605 development kit from Xilinx.

Added by Matthieu Cattin on 11 Nov 2010 at 13:22

View all news

Issue tracking

View all issues | Calendar | Gantt

Members

Manager: Matthieu Cattin
Developer: Timon Heim