DDR3 controller for Spartan6 - Overview - Open Hardware Repository

Overview

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

First prototype of the core available
The prototype of the DDR3 controller is based on the SP605 development kit from Xilinx.
Added by Matthieu Cattin about 1 year ago