Overview

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

  • Status: Release

Latest news


New release

Release 1.0 is now available with tag "1.0" in the repository.

Added by Dimitris Lampridis on 19 May 2016 at 13:07


First prototype of the core available

The prototype of the DDR3 controller is based on the SP605 development kit from Xilinx.

Added by Matthieu Cattin on 11 Nov 2010 at 13:22

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Issue tracking

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