Overview

Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.

Latest news

Initial EB master slave on hardware: the aftermath
Updates, code clean up, documentation and integration
Added by Mathias Kreider 3 months ago

Etherbone Dissector for Wireshark
Analyse EB packets in Wireshark. LUA based system independent.
Added by Mathias Kreider 6 months ago

version from workshop demo uploaded (1 comment)
-Repo file clean up done -Top level IF => std_logic_vector
Added by Mathias Kreider 10 months ago

Etherbone/FEC demo layout
Uploaded the preliminary layout for the Etherbone demo system for the April whiterabbit dev workshop. Using Altera Ethernet MAC, will be exchanged for WR Core later.
Added by Mathias Kreider 11 months ago

First draft of functional spec
Added by Julian Lewis over 1 year ago

View all news

Members

Manager: Cesar Prados, Julian Lewis, Marcus Zweig, Mathias Kreider, Stefan Rauch, Tomasz Wlostowski, Wesley W. Terpstra
Developer: Carlos Romero, Dietrich Beck, Juan David González Cobas, Marcin Zapolski, Stefan Rauch