FMC Projects » FMC ADC 100M 14b 4cha

The FMC ADC 100M 14b 4cha FMC card designed at CERN is available as a product in the catalog of the Dutch company INCAA Computers. It is the first CERN Open Hardware product that is available this way.

INCAA, the company who will make the first series production of the ADC card, reviewed the design before production. They found a problem in the schematics (the 6 Volt rail could be 6.2 Volt) and raised an issue about the PCB layout (thermal brakes too large). These issues were handled and also some minor improvements that we had still had in the Issues list are now included in the V5 design. INCAA will produce 40 of those boards for delivery in early January 2012.

After a succesful price enquiry, CERN has decided to use the company INCAA Computers in The Netherlands to produce 40 FMC ADC cards. They will be delivered in January 2012. CERN needs to finalise the production test software still before shipping a test bench to INCAA.
This card is the second CERN Open Hardware product that will be produced in quantity by industry. The first one was the SPEC FMC carrier that is being produced by Seven Solutions from Spain.
Note that according to the CERN Open Hardware Licence any company may produce these designs.

A first version of the firmware (single shot) has been tested on the SPEC along with a python test program.
The acquired ADC data are read from DDR3 via DMA.

The Oregan State University (OSU) refers to the Open ADC design on their Radio Telescope website. The aim of OSU's project is to build a small radio telescope for use in the 1 to 2 GHz range which can be used to make RF maps of interesting celestial objects and provide observational images in real time on a web site.

Ten V2 boards have arrived and are ready for testing.

One of the prototype FMC ADC cards has been donated to the non-profit institution TERA. The primary objective of the TERA Foundation is the development of radiotherapy techniques based on the use of hadron particles. The ADC card, that is designed under the Open Hardware paradigm, fulfills the needs of TERA and may in the future be used to read-out detectors used in hadron therapies.

After extensive testing of the prototype card (V1), several improvements have been made. This culminated in the V2 version of which ten will be produced, to be available on a December timescale.

The ADC board is extensively being tested. The harmonics problem seen was actually caused by the signal generator used. The I2C bus is tested and accessing the EEPROM memory, setting the sampling frequency and making temperature measurements are now possible. There appeared an issue with linearity in the 30-90 kHz region caused by offset compensation circuit. This issue, which is repeatable by simulation, is under investigation.

Since mid July we have one board plugged in on Xilinx development kit and powered. Two channels are working as limited by Xilinx development kit clock connections (we'll change our FMC connections on a V2 to cope with this). Some changes are needed to solve thermal problems. The ENOB & SNR are measured: >11 bits in all ranges. However, there seem to be still a problem with the harmonic distortion that is with -60dB somewhat higher than expected.