The FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC card in FMC (FPGA Mezzanine Card) format. By default it uses only signals from the LPC rows of the HPC connector that is mounted. The gain can be set by software in three steps: +/-50mV, +/-0.5V, +/-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of +/- 5V that is independent on the chosen gain range.
The project is divided into four sub-projects:
- Hardware design : Mezzanine board schematic and layout.
- Gateware support : HDL reference designs.
- Software support : Linux device driver, library and tools.
- Testing support : Production and functional tests.
Please refer to the corresponding sub-project for detailed information.
|max. sample rate||105 MSPS (default 100MSPS)|
|analog bandwidth||30 MHz. DC-coupled (40 MHz possible by changing eight capacitors)|
|ENOB||11, 11.5, 11.7 bit (@ +/-50mV, +/-0.5V, +/-5V range)|
|connectors||4 x LEMO 00 for signals, 1 x LEMO 00 for trigger|
|input impedance||1 kOhm / 50 Ohm - software selectable|
|gain steps|| +/-50 mV
|offset correction range||+/- 5 V for every input voltage range|
|max. gain error||+/- 1 %|
|SNR||67.7 dB, 70.8 dB, 72.2 dB (@ +/-50mV, +/-0.5V, +/-5V range)|
|FMC to carrier interface||FMC high pin count connector (HPC only used if external clock is selected)|
|Clock source|| Internal: from programmable on-board oscillator.
External: from dedicated FMC connector pins (HPC) when changing two capacitors.
- Hardware: see EDMS (CERN Electronic Document Management System) document EDA-02063.
- Gateware: see gateware sub-project releases page.
- Software: see software sub-project releases page.
- 4ch 105 Msps 14 bit ADC 30 MHz INCAA Computers, Netherlands. (standard design)
- 4ch 105 Msps 14 bit ADC 40 MHz INCAA Computers, Netherlands.
- FMC ADC 100M 14b 4cha Creotech, Poland
General question about project¶
- Erik van der Bij - CERN
|01-10-2009||Start working on project|
|25-10-2009||Functional specification written.|
|22-01-2010||FmcAdc100M14b4cha upgrade. Design revised and modified, better parameters expected.|
|10-02-2010||New design made with 3 input ranges and programmable offset.|
|04-03-2010||Improvements made, responding to design review. V1ReviewImprov|
|24-03-2010||Design review of PCB layout done. V1LayoutReview|
|09-06-2010||3 assembled boards received.|
|12-07-2010||One board plugged in on Xilinx development kit and powered. Debugging start.|
|30-07-2010||ENOB & SNR measured: >11 bits in all ranges.|
|08-09-2010||Issue with linearity in the 30-90 kHz region caused by offset compensation circuit being investigated.|
|29-09-2010||Updates to PCB made (EDA-02063-V2). Ten boards ordered. Designer left CERN.|
|07-01-2011||Ten V2 boards arrived.|
|08-03-2011||Basic HDL code written (single shot, no time stamps). Needs testing.|
|04-07-2011||V3 reviewed. V3 review. 3 prototypes will be built.|
|01-08-2011||Price Enquiry sent out for first Open Hardware production.|
|15-09-2011||V4 design made. Corrected some textual problems and one BOM item order number.|
|20-09-2011||Order for 40 cards placed with INCAA Computers (V5). Delivery in January 2012.|
|20-12-2011||Measured bandwidth is 30 MHz. 40 MHz bandwidth is possible by changing 2 capacitors per channel.|
|04-04-2012||First production received: 40 V5 cards produced by INCAA Computers.|
|12-03-2013||Release 1.0 of the fmc-adc gateware for SPEC is available.|
|19-07-2013||Firmware ported to work on the SVEC VME carrier.|
|17-01-2014||Release 3.0 of the fmc-adc gateware for SPEC and SVEC is available.|
|24-03-2014||Cards deployed in CERN's accelerator complex. Start of development to deployement: 4.5 year.|
|22-04-2014||CERN ordered 100 boards (V5-0) for delivery by 18/7/14 (20) and 19/9/14 (80).|
|07-09-2015||Over 40 installed in CERN's accelerator complex.|
Maciej Firmiarz, Matthieu Cattin, Erik van der Bij - 8 February 2017