The FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC card in FMC (FPGA Mezzanine Card) format. By default it uses only signals from the LPC rows of the HPC connector that is mounted. The gain can be set by software in three steps: +/-50mV, +/-0.5V, +/-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of +/- 5V that is independent on the chosen gain range. To see how this mezzanine can be combined with a carrier and turned into a complete system, see the system specifications page.
|max. sample rate||105 MSPS|
|analog bandwidth||30 MHz. DC-coupled (40 MHz possible by changing eight capacitors)|
|ENOB||11, 11.5, 11.7 bit (@ +/-50mV, +/-0.5V, +/-5V range)|
|connectors||4 x LEMO 00 for signals, 1 x LEMO 00 for trigger|
|input impedance||1 kOhm / 50 Ohm - software selectable|
|gain steps||+/-50 mV, +/-0.5 V, +/-5 V for full scale|
|offset correction range||+/- 5 V for every input voltage range|
|max. gain error||+/- 1 %|
|SNR||67.7 dB, 70.8 dB, 72.2 dB (@ +/-50mV, +/-0.5V, +/-5V range)|
|FMC to carrier interface||FMC high pin count connector (HPC only used if external clock is selected)|
|ADC interface||Serial LVDS, 2 pairs for each channel|
|Clock source||Internal: from programmable on-board oscillator. External: from dedicated FMC connector pins (HPC) when changing a resistor.|
- Official production documentation (schematics, PCB, etc.): EDMS: EDA-02063
- LHC Equipment name: CFFIA
- FmcAdc100m14b4cha Gateware Guide
- System specifications page (e.g. register description for use on an FMC carrier)
- Informal description of the design
- Information for designers of the FmcAdc100M14b4cha
- Software support for FMC ADC 100M 14B 4CHA (Project)
- Production Test Suite (Project)
- Frequently Asked Questions
- Hardware: FMCADC100M14b4cha V5 - EDA-02063-V5-0
- Gateware: Releases
- Linux driver: see Software support for FMC ADC 100M 14B 4CHA (Project)
- 4ch 105 Msps 14 bit ADC 30 MHz INCAA Computers, Netherlands. (standard design)
- 4ch 105 Msps 14 bit ADC 40 MHz INCAA Computers, Netherlands.
- FMC ADC 100M 14b 4cha Creotech, Poland
General question about project¶
- Erik van der Bij - CERN
|01-10-2009||Start working on project|
|25-10-2009||Functional specification written.|
|23-11-2009||Selection of components, waiting for schematic symbols.|
|02-12-2009||Work on the FmcAdc100M14b4ch_a is suspended, because estimated performance wasn't reached.|
|18-12-2009||Specification and schematic of new version has been added.|
|22-01-2010||FmcAdc100M14b4cha upgrade. Design revised and modified, better parameters expected.|
|10-02-2010|| New design made with 3 input ranges and programmable offset.
Need to finalise local clock circuit before PCB layout can start.
|24-02-2010||Draft PCB layout done. Design document being written. Design review planned for 2 March.|
|02-03-2010||Design review of schematics done. Review02032010|
|04-03-2010||Improvements made, responding to design review. Review02032010_improvements|
|19-03-2010||PCB review planned for 24 March 2010.|
|24-03-2010||Design review of PCB layout done. Review24032010|
|25-03-2010|| Small changes involved to the schematic (to make routing easier),
PCB partially updated. Review24032010_improvements
|29-03-2010||PCB updated. Waiting for Design Office's review.|
|06-04-2010||12 PCBs ordered. 3 will be mounted for prototyping.|
|12-04-2010||For availability reasons two resistor values need to be modified (120->121, 510->511). See issues.|
|06-05-2010||3 cards assembled, SMC connectors ordered but not yet available.|
|28-05-2010||SMC connectors given to workshop. Boards look really nice.|
|09-06-2010||3 assembled boards received.|
|12-07-2010||One board plugged in on Xilinx development kit and powered. Debugging start.|
|13-07-2010||Two channels working! Limited by Xilinx development kit clock connections.|
|30-07-2010||Current consumption has been measured, document is now available on the wiki.|
|30-07-2010|| Changes for the second version of the PCB documented, mainly to solve thermal problems with regulators.
Required change of DC/DC converter and inductor.
|30-07-2010||ENOB & SNR measured: >11 bits in all ranges.|
|03-08-2010||First harmonic distortion measurements made. Needs further investigation as with -60dB is higher than expected.|
|03-09-2010|| The distortion source has been found.
For further information go to Investigating the distortion source...
|03-09-2010||Thermal stability measurements made.|
|03-09-2010|| Frequency response of the anti-aliasing filter will be verified and possibly corrected.
Needs development of software that shows frequency response.
|07-09-2010|| Both I2C buses are working. Accessing memory, setting the sampling frequency and
making temperature measurements are now possible.
|08-09-2010||Issue with linearity in the 30-90 kHz region caused by offset compensation circuit being investigated.|
|20-09-2010||The schematic has been updated. All the differences for the second version are given here :PDF|
|29-09-2010||Updates to PCB made (EDA-02063-V2). Ten boards ordered. Designer left CERN.|
|22-10-2010||Found inconsistencies in BOM. Requires modifications to schematics and production files.|
|08-12-2010|| Production of ten boards of V2 will arrive before
|07-01-2011||Ten V2 boards arrived.|
|23-02-2011||First board powered up on a SPEC carrier, no smoke!|
|03-03-2011|| Trial of wave soldering of LEMO connector instead of SMC looks OK.
PCB redesign needed if want to use wave soldering.
|08-03-2011||Basic HDL code written (single shot, no time stamps). Needs testing.|
|28-03-2011||Basic HDL code tested. We're able to DMA raw adc data from DDR3 memory to the host and gnuplot them.|
|21-06-2011||Made schematics and layout modifications for V3 (see changelog).|
|22-06-2011||Project sent to DEM for front panel modification and production file generation. Ready on 24-06-2011.|
|27-06-2011||V3 ready for review.|
|04-07-2011||V3 reviewed. V3 review. 3 prototypes will be built.|
|01-08-2011||Price Enquiry sent out for first Open Hardware production.|
|12-08-2011||Firmware being finalised. Made re-usable for use in the fmc-adc-100k16b8cha, a slower ADC mezzanine.|
|18-08-2011||Design of a tester board.|
|30-08-2011||Production test software being written.|
|12-09-2011||Price Enquiry finished. Received replies from several companies. Order for 40 cards being made.|
|15-09-2011||V4 design made. Corrected some textual problems and one BOM item order number.|
|20-09-2011||Order for 40 cards placed with INCAA Computers (V5). Delivery in January 2012.|
|10-10-2011||Useful feedback from INCAA Computers made us improve the design as V5.|
|02-12-2011||Firmware getting stable. Demo oscilloscope program in Python written.|
|20-12-2011||Measured bandwidth is 30 MHz. 40 MHz bandwidth is possible by changing 2 capacitors per channel.|
|10-01-2012|| Expect delivery of 40 cards
|04-04-2012||First production received: 40 V5 cards produced by INCAA Computers.|
|05-02-2013||Firmware development on-going. In parallel a driver is being written. Expect a release in April 2013|
|12-03-2013||Release 1.0 of the fmc-adc gateware for SPEC is available.|
|28-03-2013||Release 1.1 of the fmc-adc gateware for SPEC is available.|
|19-07-2013||Firmware ported to work on the SVEC VME carrier.|
|29-07-2013||Release 2.0 of the fmc-adc gateware for SPEC is available.|
|29-07-2013||Release 1.0 of the fmc-adc gateware for SVEC is available.|
|17-01-2014||Release 3.0 of the fmc-adc gateware for SPEC and SVEC is available.|
|24-03-2014||Cards deployed in CERN's accelerator complex. Start of development to deployement: 4.5 year.|
Maciej Firmiarz, Matthieu Cattin, Erik van der Bij - 27 March 2014