Functional system specifications for the PCIe carrier version¶
| Parameter | Value |
|---|---|
| Max. sample rate | 100 MSPS |
| Available sampling rates | Programmable 16-bit divider off 100 MHz |
| Sampling word width | 14 bits |
| ENOB | > 11 bits |
| Channels | 4 |
| Connectors | 4 x LEMO for signals, 1 x LEMO for trigger |
| Analog bandwidth | 30 MHz, DC-coupled |
| Input impedance | 1kOhm / 50 Ohm - software selectable |
| Gain steps | +/-50mV, +/-0.5V, +/-5V for full scale |
| Offset correction range | +/- 5V for every input voltage range |
| Max. gain error | +/- 1% |
| Clock source: | External (from dedicated FMC connector pins) or from programmed on-board generator (fixed or tracking external reference) |
| Trigger | External (LVTTL) or internal with programmable slope, level and delay. Multi-trigger support with programmable hold-off. |
| Sampling memory | 32 MSamples per channel |
| Card to host sample transfer | Chained DMA engine over PCIe |
| Data transfer rate over PCIe | > 50 MB/s |
| Interrupts | Trigger, end of shot, temperature alarm |
| Time stamping | UTC for trigger and START/STOP commands |
Technical specifications for the PCIe carrier version¶
See Technical HDL specification for PCIe ADC100M14b4cha system.
Memory map¶
This is a preliminary mapping of the memory. It might change in the future.
BAR0 (1MB):
| Wishbone Cores | ||||
|---|---|---|---|---|
| Offset (bytes) | Description | Peripherals | Internal mapping | Status |
| 0x00000 | DMA Controller | DMA config. and status | Registers | Available |
| 0x10000 | Carrier SPI master | DAC control (driving VCXO) | Registers | Not implemented |
| 0x20000 | Carrier 1-wire master | Thermometer + unique ID | Registers | Available |
| 0x30000 | Carrier CSR | PLL, DDR status, LED control, etc... | Registers | Available |
| 0x40000 | UTC core | Trigger, acq time-tags | Registers | Available |
| 0x50000 | Interrupt controller | Enable mask, irq source | Registers | Available |
| 0x60000 | Mezzanine system management I2C master | EEPROM (FMC standard) | Registers | Available |
| 0x70000 | Mezzanine SPI master | ADC, DAC (for DC offset) | Registers | Available |
| 0x80000 | Mezzanine I2C master | Oscillator (sampling clock) | Registers | Available |
| 0x90000 | Mezzanine ADC core CSR | ACQ state machine, input range, trigger, etc... | Registers | Available |
| 0XA0000 | Mezzanine 1-wire master | Thermometer + unique ID | Registers | Available |
HDL development Project Status¶
| Date | Event |
|---|---|
| 25-04-2010 | Start working on project. |
| 04-05-2010 | Preliminary functional specs ready for discussion. |
| 23-09-2010 | Technical specification ready and usable for implementation of HDL development. |