This project is on hold
The FmcAdc250M12b2cha is a 2 channel 250MSPS 12 bit ADC card in FMC (FPGA Mezzanine Card) format using an LPC connector. The gain can be set by software in three steps: +/-50mV, +/-0.5V, +/-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of +/- 5V that is independent on the chosen gain range. To see how this mezzanine can be combined with a carrier and turned into a complete system is TBD (information follows as soon as possible).
|Max. sample rate||250 MSPS|
|Analog bandwidth||DC - 80 MHz (73 MHz at maximum gain)|
|ENOB||11 bit (spec ADC only)|
|Connectors|| 2 x LEMO 00 for signal inputs 1 kOhm / 50 Ohm
2 x LEMO 00 for signal inputs 1 MOhm
1 x LEMO 00 for trigger
|Input impedance|| Inputs 1 & 3 : 1 kOhm / 50 Ohm - software selectable
Inputs 2 & 4 : 1 MOhm
|Gain steps||+/-50 mV, +/-0.5 V, +/-5 V for full scale|
|Offset correction range||+/- 5 V for every input voltage range|
|Max. gain error||+/- 1 %|
|SNR||65.5 dB (spec ADC only)|
|FMC to carrier interface||FMC low pin count connector|
|ADC interface||Serial LVDS, 6 pairs DDR for each channel|
|Clock source||Programmable on-board oscillator|
- Block diagram - PDF file:
- Schematic diagram - PDF file:
- PCB drawings - PDF file:
- Bill of materials - Excel file:
- Altium (summer '09) project file:
- Fabrication documents (gerber, nc-drill, pick and place, BOM):
- Daniel Florin - Physik Institut, Universitaet Zuerich
|09-01-2012||Start working on project.|
|18-01-2012||Functional specification defined, first release of electrical block diagram made.|
|08-02-2012||First release of electrical schematic diagram ready for review.|
|15-02-2012|| Simulated three slightly different approaches for the analog input stages.
Details see http://www.ohwr.org/attachments/download/1010/FmcAdc250M12b2cha_AnalogInputStage.zip.
|16-02-2012||Separate inputs with HiZ input buffers added.|
|05-03-2012||PCB version 1.00 ready for production. 3D previews of board: Top / Bottom|
|15-05-2012||Minor changes done, PCB version remains 1.00|
|23-09-2015||Project is on hold. No further developments planned.|
- Fundamentals of Sampled Data Systems - Overview, Analog Devices
- From EETimes Europe
- ADC Tutorials, Analog Devices
- From Data Converter Tutorials, Analog Devices
- Optimizing SAR ADC performance by proper PCB layout (recommendations may be used in a future version of the design).
- Seven Steps to Successful Analog-to-Digital Signal Conversion (Noise calculation for proper signal conditioning) - Understand how to balance gain blocks and noise, 2010, R. Moghimi, Analog Devices.
- Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so You Don't Get Lost in the Noise Floor, W. Kester, Analog Devices
- DC-coupled, single-to-differential design solutions using fully differential amplifiers-, Michael Steffes, Sr. Applications Manager, Intersil Corp.
- Calibrating amplifiers and ADCs in SoCs, M. Ganesh Raaja & Pushek Madaan, Cypress Semiconductor Corp., 2012. Referred to from EEtimes. The FmcAdc100M14b4cha implements double point calibration in the production test, using an external calibration voltage. It should be possible to implement Correlated Double Sampling (CDS) to dynamically compensate for offset errors. No internal calibration voltage is present.
Daniel Florin - 15 May 2012 (status update 23 September 2015)