Project description

This project is on hold

The FmcAdc250M12b2cha is a 2 channel 250MSPS 12 bit ADC card in FMC (FPGA Mezzanine Card) format using an LPC connector. The gain can be set by software in three steps: +/-50mV, +/-0.5V, +/-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of +/- 5V that is independent on the chosen gain range. To see how this mezzanine can be combined with a carrier and turned into a complete system is TBD (information follows as soon as possible).

Specifications (PRELIMINARY)

Parameter Value
Max. sample rate 250 MSPS
Analog bandwidth DC - 80 MHz (73 MHz at maximum gain)
Bits/sample 12 bit
ENOB 11 bit (spec ADC only)
Channels 2
Connectors 2 x LEMO 00 for signal inputs 1 kOhm / 50 Ohm
2 x LEMO 00 for signal inputs 1 MOhm
1 x LEMO 00 for trigger
Input impedance Inputs 1 & 3 : 1 kOhm / 50 Ohm - software selectable
Inputs 2 & 4 : 1 MOhm
Gain steps +/-50 mV, +/-0.5 V, +/-5 V for full scale
Offset correction range +/- 5 V for every input voltage range
Max. gain error +/- 1 %
SNR 65.5 dB (spec ADC only)
FMC to carrier interface FMC low pin count connector
ADC interface Serial LVDS, 6 pairs DDR for each channel
Clock source Programmable on-board oscillator

Project documents


FmcAdc250M12b2cha V1.00



Date Event
09-01-2012 Start working on project.
18-01-2012 Functional specification defined, first release of electrical block diagram made.
08-02-2012 First release of electrical schematic diagram ready for review.
15-02-2012 Simulated three slightly different approaches for the analog input stages.
Details see
16-02-2012 Separate inputs with HiZ input buffers added.
05-03-2012 PCB version 1.00 ready for production. 3D previews of board: Top / Bottom
15-05-2012 Minor changes done, PCB version remains 1.00
23-09-2015 Project is on hold. No further developments planned.

Useful references

Daniel Florin - 15 May 2012 (status update 23 September 2015)