Project description

The FMC DEL 1ns 4cha delay module will take in a TTL trigger signal and will send it out to four different outputs. The delay from the trigger input to each of the outputs can be set independently in a range from 600 ns to 120 seconds. It is implemented using a dedicated time-to-digital converter IC from the European company Acam.

Top view of the FMC Delay card
Bottom view


Specification overview

Parameter Value
Channels 1 trigger input, 4 outputs
Signal connectors LEMO 00 for all signals
FMC connector Low Pin Count (LPC)
Signal level TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate
Operating modes Pulse delay: on trigger, generates a pulse or series of pulses of given width and repetition rate on chosen outputs after a certain time programmed by the user.
Single channel TDC: time tags incoming trigger pulses available via a circular buffer.
Pulse generator: produces a pulse or a series of pulses of arbitrary length and repetition rate starting at a given UTC/TAI time.
Minimum input pulse width 100 ns. Pulses below 24 ns are ignored.
Maximum input pulse rate 1 MHz (minimum pulse spacing: 1 us)
Output pulse width 250 ns - 1 s (10 ps resolution), 50ns - 1 s (pulse generation mode only, 4 ns resolution)
Output pulse spacing 250 ns - 1 s (10 ps resolution), 50ns - 1 s (pulse generation mode only, 4 ns resolution)
Trigger to output delay 600 ns (min) to 120 seconds (max). Independent setting for each channel.
Output pulse repeat count (train generation) 1 - 65536 pulses or infinity (continuous mode)
Timebase accuracy ± 2.5 ppm
The timebase from a local TCXO on FMC card needs calibration. The 2.5 ppm accuracy is the one of the on-board TCXO. Cesium-quality accuracy will be reached when used on a White Rabbit enabled FMC carrier.
TDC Resolution 28 ps
TDC Precision (std. dev) 55 ps
Delay accuracy Baseline: < 300 ps average, < 1 ns peak-to-peak (minimum delay setting of 600 ns).
Accuracy is as good as the time base, e.g. for a delay of 1 s using internal time base, the worst case error will be (2.5 ppm x 1 s) = 2.5 us. The accuracy can be greatly improved by locking the card to GPS/Cesium clock source through White Rabbit.
Time tag buffer 1024-entries circular buffer with time tags for input/output pulses. Buffer interrupt (with timeout/threshold coalescing)
Power consumption 7 Watt (200 mA from 12V, 1.5 A from 3V3)

Detailed project information



Commercial producers

General question about project

Project Status

Date Event
22-04-2010 Start working on project.
30-04-2010 First meeting with N. Voumard to fine-tune functional specs.
20-05-2010 Second functional specs meeting with the ABT team.
11-06-2010 Order 4384595 made for design of the module.
15-06-2010 Final functional specification review meeting held. Resulted in minor modifications.
30-06-2010 Technical specification draft finished.
17-08-2010 First schematics review held. ReviewFineDelayFMC17082010
03-09-2010 Schematics revised. Waiting for a new design review.
10-11-2010 Second schematics review held. ReviewFineDelayFMC10112010
12-11-2010 Comments on review received. Re-commented on it. FMC10112010_improvements v5
25-11-2010 Updated schematics and comments received. ReviewFineDelayFMC10112010_improvements
25-11-2010 Comments on updated schematics. ReviewFineDelayFMC25112010
30-11-2010 Updated schematics and comments received. ReviewFineDelayFMC25112010_improvements
13-12-2010 First version of PCB layout expected by 17 December.
14-01-2011 Spec change for minimum delay: 500 ns. PCB layout almost finished, waiting for some symbols.
18-01-2011 PCB layout received. Review on 19-01-2011.
18-01-2011 Changelog for the PCB/schematics published: Changelog_19012010
20-01-2011 PCB review held. V1 layout ready (SVN revision: 18) Changelog_20012011
28-01-2011 Empty PCB should arrive on 1 February. Requested design office to review files.
03-02-2011 Prototype PCB assembled and ready for HDL development. ID EEPROM works.
14-02-2011 Design being reviewed by CERN's design office.
21-02-2011 HDL development on-going.
02-03-2011 Returned corrections in schematics to design office.
18-03-2011 Design checked and available in EDMS.
19-04-2011 Rather high jitter in prototype. Will improve layout of supply to ACCAM chip.
05-05-2011 V2 schematics and layout available for review: Changelog_05052011
06-05-2011 V2 review held. Reduce number of R values, no large ceramic C, 20 MHz osc instead of 25 MHz.
08-06-2011 Files sent to CERN's design office for review and front-panel design.
14-07-2011 V2 design ready. Will produce 4 prototypes, after correcting OHL licence and removal of CERN logo.
16-08-2011 PCB ready by 19-08-2011. Assembly can start.
31-08-2011 Received assembled prototype of V2.
02-09-2011 V2 works.
16-11-2011 V2 demoed on SPEC. Considering changing output driver to have less cross-talk.
09-01-2012 V3 proto with changed output driver being tested. Preparing price enquiry.
26-01-2012 Price enquiry sent out. Deadline 24 February. 40 cards expected by 24 August.
03-02-2012 In parallel assemble 10 boards for urgent project.
24-02-2012 One card sent for writing Linux driver. Firmware available, but needs finalisation.
01-03-2012 Third schematics and PCB review held. ReviewFineDelayFMC02032012
07-03-2012 Order placed with INCAA for 40 cards (V4-0). Delivery: preseries (10) end June; series (30) end August.
15-03-2012 INCAA reviewed the design. Modifications will be made. ReviewFineDelayFMC15032012
28-03-2012 New version 4-0 given to design office for verification.
29-03-2012 Received 15 V3 boards for use in CNGS and prototyping purposes.
04-06-2012 During running in CNGS found two issues that need change of components (515, 516)
17-08-2012 Received 10 pre-series cards from order to INCAA.
10-09-2012 CERN entered the modules in the stock for later use in LHC and other accelerators.
27-09-2012 Order placed with INCAA for additional 30 cards (V4-0).
15-01-2013 30+30 cards received at CERN (in addition to the 10 pre-series cards).
06-02-2013 Change of spec: Maximum input pulse rate lowered to 1 MHz and minimum pulse spacing increased to 1 us.
18-06-2013 V5-1 of design published. Improves jitter (740). Issue 608 not handled.
20-06-2013 Spec change for minimum delay: 600 ns (was 500 ns).
03-09-2013 Ordered 10 additional cards for CERN EN/ICE.
27-09-2013 A third company is producing and supporting the card.
27-05-2014 V6-0 of design published, contains manufacturability improvements (issue 770).
13-06-2014 Order placed for 80 cards (V6-0): 30 by 26/9/14, 50 by 28/11/14.
27-10-2014 V6-1 design required (for new productions only) to solve issue.
18-12-2014 Gateware v.2.1 released.
19-01-2015 V6-1 hardware design released.

Tomasz Wlostowski, Erik van der Bij - 8 February 2017