History

Project description

The FMC DEL 1ns 4cha delay module will take in a TTL trigger signal and will send it out to four different outputs. The delay from the trigger input to each of the outputs can be set independently in a range from 500 ns to 120 seconds. It is implemented using a dedicated time-to-digital converter IC from the European company Acam.


Top view of the FMC Delay card with SMC connectors. Final design will use LEMO 00 connectors
Bottom view

Functional system specifications

Technical specification

  • Baseline solution: TDC at the inputs followed by coarse count in the FPGA and fine delay chips at the outputs. To be considered for improving jitter: monolithic FFs in the FMC, before the fine delay chips. Continuous calibration of fine delay chips might be needed to compensate for Process-Voltage-Temperature (PVT) effects. The timebase is from a local TCXO on FMC card and needs calibration. The 4ppm accuracy will only be reached when used on a White Rabbit enabled FMC carrier.

Detailed project information

Contacts

Commercial producer

General question about project

Project Status

Date Event
22-04-2010 Start working on project.
30-04-2010 First meeting with N. Voumard to fine-tune functional specs.
20-05-2010 Second functional specs meeting with the ABT team.
11-06-2010 Order 4384595 made for design of the module.
15-06-2010 Final functional specification review meeting held. Resulted in minor modifications.
30-06-2010 Technical specification draft finished.
17-08-2010 First schematics review held. ReviewFineDelayFMC17082010
03-09-2010 Schematics revised. Waiting for a new design review.
10-11-2010 Second schematics review held. ReviewFineDelayFMC10112010
12-11-2010 Comments on review received. Re-commented on it. FMC10112010_improvements v5
25-11-2010 Updated schematics and comments received. ReviewFineDelayFMC10112010_improvements
25-11-2010 Comments on updated schematics. ReviewFineDelayFMC25112010
30-11-2010 Updated schematics and comments received. ReviewFineDelayFMC25112010_improvements
13-12-2010 First version of PCB layout expected by 17 December.
14-01-2011 Spec change for minimum delay: 500 ns. PCB layout almost finished, waiting for some symbols.
18-01-2011 PCB layout received. Review on 19-01-2011.
18-01-2011 Changelog for the PCB/schematics published: Changelog_19012010
20-01-2011 PCB review held. V1 layout ready (SVN revision: 18) Changelog_20012011
28-01-2011 Empty PCB should arrive on 1 February. Requested design office to review files.
03-02-2011 Prototype PCB assembled and ready for HDL development. ID EEPROM works.
14-02-2011 Design being reviewed by CERN's design office.
21-02-2011 HDL development on-going.
02-03-2011 Returned corrections in schematics to design office.
18-03-2011 Design checked and available in EDMS.
19-04-2011 Rather high jitter in prototype. Will improve layout of supply to ACCAM chip.
05-05-2011 V2 schematics and layout available for review: Changelog_05052011
06-05-2011 V2 review held. Reduce number of R values, no large ceramic C, 20 MHz osc instead of 25 MHz.
08-06-2011 Files sent to CERN's design office for review and front-panel design.
14-07-2011 V2 design ready. Will produce 4 prototypes, after correcting OHL licence and removal of CERN logo.
16-08-2011 PCB ready by 19-08-2011. Assembly can start.
31-08-2011 Received assembled prototype of V2.
02-09-2011 V2 works.
16-11-2011 V2 demoed on SPEC. Considering changing output driver to have less cross-talk.
09-01-2012 V3 proto with changed output driver being tested. Preparing price enquiry.
26-01-2012 Price enquiry sent out. Deadline 24 February. 40 cards expected by 24 August.
03-02-2012 In parallel assemble 10 boards for urgent project.

Erik van der Bij - 3 February 2012

side_a_s.JPG (98.9 kB) Tomasz Wlostowski, 04/02/2011 16:10

side_b_s.JPG (116 kB) Tomasz Wlostowski, 04/02/2011 16:10