Driver developers information

Memory map

Fine Delay Core internals

This is the mapping of the internal FD core components with respect to the core's base address

Wishbone Cores
Offset (bytes) Description Peripherals Internal mapping Status
0x000 Main Registers FD Core shared control registers (TDC and global configuration) wbgen2 doc Available
0x100 Channel 1 Registers FD Core output channel 1 control registers (delay/pulse gen settings) wbgen2 doc Available
0x200 Channel 2 Registers FD Core output channel 2 control registers (delay/pulse gen settings) wbgen2 doc Available
0x300 Channel 3 Registers FD Core output channel 3 control registers (delay/pulse gen settings) wbgen2 doc Available
0x400 Channel 4 Registers FD Core output channel 4 control registers (delay/pulse gen settings) wbgen2 doc Available
0x500 FMC 1-wire master Thermometer + unique ID (on the respective FMC) registers Available

SPEC carrier bitstream

This is the mapping of the top level SPEC interconnect in the v1.0 release firmwares. Future releases will have all blocks starting at offset 0x00000 (update of Gennum core). All offsets are referenced to PCI BAR0.

Wishbone Cores
Offset (bytes) Description Peripherals Internal mapping Status
0x80000 Fine Delay Core FD Core for FMC 1 see table above Available
0xc0000 White Rabbit PTP core WR PTP core, provides distributed synchronization Wiki Available

This is the proposed mapping of the top level SPEC interconnect in the v2.0 release firmwares. All offsets are referenced to PCI BAR0.

Wishbone Cores
Offset (bytes) Description Peripherals Internal mapping Status
0x00000 SDB descriptor SDB descriptor base, used for automagic enumeration of the builtin cores. see SDB documentation Available
0x80000 Fine Delay Core FD Core for FMC 1 see table above Available
0x90000 Vectored Interrupt Controller Interrupt controller Wiki Available
0xc0000 White Rabbit PTP core WR PTP core, provides distributed synchronization Wiki
Available
VIC Interrupt assignment
IRQ line Description
0 Fine Delay Core multiplexed interrupt

SVEC carrier bitstream

This is the mapping of the top level SVEC interconnect (internal release for driver development purposes). All offsets are referenced to the VME base address set in the VME64x core's CSR space. Card supports A24/A32/D32 accesses ONLY.

Wishbone Cores
Offset (bytes) Description Peripherals Internal mapping Status
0x00000 SDB descriptor SDB descriptor base, used for automagic enumeration of the builtin cores. see SDB documentation Available
0x10000 Fine Delay Core (FMC1) FD Core for FMC 1 see table above Available
0x20000 Fine Delay Core (FMC2) FD Core for FMC 2 see table above Available
0x30000 Vectored Interrupt Controller Interrupt controller Wiki Available
0x40000 White Rabbit PTP core WR PTP core, provides distributed synchronization Wiki Available
VIC Interrupt assignment
IRQ line Description
0 Fine Delay Core (FMC1) multiplexed interrupt
1 Fine Delay Core (FMC2) multiplexed interrupt