Fine Delay Functional Specifications¶
The FMC Delay 1ns-4cha is an FPGA Mezzanine Card (FMC - VITA 57 standard), whose
main purpose is to produce pulses delayed by a user-programmed value with respect to the
input trigger pulse. The card can also work as a Time to Digital converter (TDC) or as a
programmable pulse generator triggering at a given TAI time.
Modes of operation¶Fine Delay can work in one or more of the following modes:
- Pulse Delay: produces one or more pulse(s) on selected outputs a given time after an input
trigger pulse (fig. 1a)
- Pulse Generator: produces one or more pulse(s) on selected outputs starting at an absolute
time value programmed by the user (fig. 1b). In this mode, time base is usually provided
by the White Rabbit network.
- Time to Digital Converter: tags all trigger pulses and delivers the timestamps to the user’s
Fig 1. Illustration of Delay/Pulse Generator mode operation.
Modes (pulse delay/generator) can be selected independently for each output. For example, one
can configure the output 1 to delay trigger pulses by 1 us, and the output 2 to produce a pulse
at the beginning of each second. The TDC mode can be enabled for the input at any time and
does not interfere with the operation of the channels being time tagged.
- 1 trigger input (LEMO 00)
- 4 pulse outputs (LEMO 00)
- 2 LEDs
- Carrier communication via 160-pin Low Pin Count FMC connector
- TTL/LVTTL levels, DC-coupled. Reception of a trigger pulse is indicated by blinking the
"TRIG" LED in the front panel.
- 2 kOhm or 50 Ohm input impedance (programmable via software). 50 Ohm termination is
indicated by the "TERM" LED in the front panel.
- Power-up input impedance: 2 kOhm.
- Protected against short circuit, overcurrent (> 200 mA) and overvoltage (up to +28 V).
- Maximum input pulse edge rise time: 20 ns.
- TTL-compatible levels DC-coupled: Voh = 3 V, Vol = 200 mV (50 Ohm load), Voh = 6
V, Vol = 400 mV (high impedance).
- Output impedance: 50 Ohm (source-terminated)
- Rise/fall time: < 2 ns (10% - 90%, 50 Ohm load)
- Power-up state: LOW (2 kOhm pulldown), guaranteed glitch-free.
- Protected against continuous short circuit, overcurrent and overvoltage (up to +28 V).
- Used power supplies: P12V0, P3V3, P3V3 AUX, VADJ (voltage monitor only).
- Typical current consumption: 200 mA (P12V0) + 1.5 A (P3V3).
- Power dissipation: 7 W. Forced cooling is required.
Fig 2. Fine Delay timing parameters explanation.
- Onboard oscillator accuracy: +/- 2.5 ppm (i.e. max. 2.5 ns error for a delay of 1 ms).
- When using White Rabbit as the timing reference: depending on the characteristics of the
grandmaster clock and the carrier used. On SPEC v 4.0 FMC carrier, the accuracy in WR mode is better
than 1 ns.
- Minimum pulse width:
tIW= 50 ns. Pulses below 24 ns are rejected.
- Minimum gap between the last delayed output pulse and subsequent trigger pulse:
- Input TDC performance: 400 ps peak-peak accuracy (trigger input to time base), 27 ps resolution, 70 ps trigger-to-trigger rms
jitter (measured at 500 kHz pulse rate)
- Resolution: 10 ps.
- Accuracy (pulse generator mode): 300 ps p-p.
- Train generation: trains of 1-65536 pulses or continuous square wave up to 10 MHz.
- Output-to-output jitter (outputs programmed to the same delay): 10 ps rms.
- Output-to-output jitter (outputs programmed to to different delays, worst case): 30 ps rms.
- Output pulse spacing (
TSP) : 100 ns - 16 s. Adjustable in 10 ps steps when both
TGAP> 200 ns. Outside that range,
TSPresolution is limited to 4 ns.
- Output pulse start (
tSTART) resolution: 10 ps for the rising edge of the pulse, 10 ps for
subsequent pulses if the condition above is met, otherwise 4 ns.
- Delay accuracy: < 300 ps average, < 1 ns peak-to-peak. (input-output, for the minimum delay setting of 600 ns).
Accuracy is as good as the time base, e.g. for a delay of 1 s and internal time base, the worst case error will be (4 ppm x 1 s) = 4 us. Accuracy can be greatly improved by locking the card to GPS/Cesium clock source through White Rabbit.
- Trigger-to-output jitter: 80 ps rms.
- Trigger-to-output delay: minimum
TDLY= 600 ns, maximum
TDLY= 120 s.
- Maximum trigger pulse rate:
TGAP) + 100 ns, where
N= number of
- Trigger pulses are ignored until the output with the biggest delay has finished generation
of the pulse(s). Explanation
Mechanical/Environmental¶Mechanical and environmental specs:
- Format: FMC (VITA 57), with rear zone for conduction cooling
- Operating temperature range: 0 - 90 deg C.
- Carrier connection: 160-pin Low Pin Count FMC connector