V4 Schematics and layout review held on 1 March 2012¶
Present: E.van der Bij, M. Cattin, E. Gousiou, C. Gil Soriano, T. Wlostowski - CERN
Files used for the review are in revision 828b9fab in the repository -> circuit_board
A working V3 prototype was shown. The review was not prepared and was done during the meeting.
- The Voh level of the outputs is too high (6.5V). Although it is understood that this is to keep a 5V level when terminated at 50 Ohm, the level will be too high when not terminated and may burn inputs.
- Reduce the output level to maximum 5.0V when unterminated.
- Add decoupling capacitors for use near the FMC connector.
- Do put decoupling capacitors around/under the FMC connectors, like you would do for an actual component (each power pin). This provides a better supply to the mezzanines and also if there is a AC return path that is coupled to a Vcc line (as the signal line is close to it), will get a way to the Gnd plane via these C's.
- Replace the standard tantalium capacitors by Sanyo Poscap capacitors.
- The reason is that the board runs very hot (90 degrees has been seen when used without any forced airflow) and the lifetime of the standard tantaliums may seriously be reduced.
- Likely the three types of large capacitors may be reduced to only two types.
- Some cosmetic changes in the schematics.
- Remove the cuts in the ground plane near the LEMO connectors to have a more direct return path to the front-panel screws and let rush currents not flow through the active part of the board.
- Verify the solder mask to have no single large hole under one of the ICs.
Erik van der Bij - 2 March 2012