ReviewFineDelayFMC10112010

Schematics layout review held on 10 November 2010

Present: N. Voumard, P. Alvarez Sanchez, M. Cattin, E.van der Bij - CERN

Files used for the review:
http://www.ohwr.org/projects/fmc-delay-1ns-8cha/repository/revisions/7/show/trunk/circuit_board/fmc-delay-1ns-8cha/Schematics


General
  1. "No DRC" crosses on unused inputs and outputs are not systematically placed.
  2. Check the BOM to see if the number of components can be reduced. E.g. no 100uF, R values, package types.
Page 1
  1. Switching in the 50 Ohm input termination should not use a jumper as it will not be accessible. Make it programmable via the FMC connector.
  2. TRIGSEL should not use a jumper as this will not be accessible. Make it programmable via the FMC connector.
  3. The LEDs should not be directly on Trigger_select and termination. Run both from the FMC connector. Use for one would be to show incoming triggers and therefore needs to come from the FMC connector (extended pulse).
  4. Remove note with text "Add termination jumper".
  5. Move R24A out of page 8, move it to top level, page 1. Otherwise it will be assembled twice.
  6. Add a note that Vref needs to be 2.5V.
Page 2
  1. Drive the VCXO (OSC1) with a DAC, like is used on the SPEC card. This way we can use the board on other carriers and use the White Rabbit tricks.
  2. Define the type number of OSC1. Use same as on the SPEC card.
  3. Pin 36, FPGA_TDC_REF_CLK: add 100 Ohm series resistor as is 3V3 signalling going to 2.5V FMC.
  4. Add 100nF capacitors on +3.3C_PLL. Consider removing the 1nF.
  5. Add testpoints on LD, STATUS, REFMON (IC4).
  6. Cleanup unused pins.
    • OUT3, remove wires.
    • Can pin 63 be left open, or better ground it?
    • Add no DRC marker on unused pins.
  7. Document design of the loop filter. With the resistors, it is different from the datasheet page 34. Also document the calculation of capacitor values.
Page 3
  1. Wrong connections of VREF_A_M2C, Gnd, PRSNT_M2C_L: they are on the wrong row (H vs G). Check G1-G3, H1-3
  2. VREF (H1) should be left unconnected. It is not used.
  3. PRSNT_M2C_L (H2) should be connected directly to Gnd.
  4. Mark that Vref needs to be 2.5V (also on top page, page 1).
  5. If need to make available pins, may remove EXT_CLK_P/N as we will use the internal clock in every case.
  6. Remove text "Text" below J6A.
  7. Mark clearly row C, D, G, H (bold below each row)
  8. Put page in landscape so that rows can be put in same order as in VITA specification.
  9. Cleanup DRC markers (some in middle of the line, others missing. Actually not clear which lines are not used.
  10. Grounding of front-panel and standoffs near connector: Replace 1 MOhm by 0 Ohm, remove 22nF. Verify that front-left is connected to stand-off left. Likewise with right side.
    • Is design as is retained on the ADC card.
Page 4
  1. Check if double LED used is same as on ADC: DIALIGHT 571-0122-100F (dual 2mm Green LEDs CBI Indicator (with positioning pins).
  2. Use same MOS transistor as used for the input termination switch instead of Transistor. Saves a BOM item.
  3. GA0 and GA1 of IC22 are correct. GA1 and GA0 of IC13 need to be swapped?
  4. Add note on adressing of the two components.
  5. Add note that TPS3307 is a temperature sensor.
Page 5
  1. Remove inductor L5. I.e. the 3.3V plane will be powered straight from the FMC 3P3V power supply.
    • May require rename of all +3.3V to 3P3V. Verify if no +3.3V symbols left.
  2. Add note about treshold voltages of IC16.
Page 6
  1. The input level is not TTL (as was specified), but is LVTTL. Now when entering a 5V signal, the diodes will continuously conduct, while not being protected in any way. The fuse will not trigger (or even worse, it maybe even will switch off) and there is no resistor limiting the current.
  2. Can the input fuse handle the bandwidth and short pulses? It is a device made for power use, not signal use. Dependent how it behaves it may heat up and increase resistance dependent on the input signal it receives and therefore may introduce a phase delay. Any experience with this?
  3. What is the footprint of the fuse? Can it be replaced by a simple resistor when needed?
  4. The inputs of the input multiplexer IC17 TS3usb221 (FET switch) are wrongly connected (signal 1D- can only go to unconnected D- output).
  5. Consider to use a multiplexer with output buffer (the one now used is a FET switch) so that the output level is well defined.
  6. The 47 Ohm input termination is in 1206 package and likely is too small to dissipate if a continuous high level is used. Check the fast ADC card , uses 47 Ohm in 2512 package. See also ADC issue.
  7. IC14A is a D-register. The reviewers think a simple buffer would be better. Explain why a register is used here.
  8. Symbol MC100EPT20DTG (IC5) has the flash in the wrong direction on input pin 7.
  9. Symbol 74AC74M (e.g. IC14) has CLR and PR texts rotated and overlapping.
Page 7
  1. Add a note in the schematic explaining the power supply compensation circuit of the TDC-GPX. Notably the supply VDD_TDC is not part of the diagram used in the datasheet and very different from using a Schottky diode. Consider prototyping without the 'compensation' on VDDC_TDC.
  2. Even when the VDDC_TDC supply is 'compensated' like VDDC-H/O, it seems that C22 and R16 are connected to the wrong place and should be connected to the ADJ input of the regulator.
  3. Add a note on the nominal voltage of VDD_TDC and VDDC_H/O
  4. Using 100uF as decoupling is overkill. See also the App note Reduced Decoupling where they even reduce the 47uF. The 100uF is not recommended in the datasheet and there are anyway already many 47uF capacitors.
  5. Suggest to add 100nF decoupling C's like normally is used. On VDD_TDC and VDDC_H/O.
  6. Inputs of TDC-GPX not used correctly. See table starting at page 11 of the datasheet. Verify all levels as it seems to be critical (some need straight Gnd, others via 10KOhm, even a line with an exclamation mark in the datasheet :-)
    • E.g. Alutrigger and Tstop5-8 need a 10KOhm to Gnd instead of direct connection.
    • StopDis3 should be grounded.
    • Tstop5-8 need 10kOhm.
  7. For readability use similar schematic layout for termination of TDC_STOP as used for TDC_START.
Page 8, twice
  1. Disconnect VBB of all chips.
    • May only be used within a single IC (now all VBB's connected together).
  2. Connect R and S to another level. VBB is exactly in the middle of Vil and Vih, so not suitable.
    • Move R24A out of page 8, move it to top level, page 1. Otherwise it will be assembled twice.
    • Remove text near R24A ("R24 is optional").
Page 9
  1. Output is LVTTL. Specification and user requires real TTL drive. Replace output driver.
  2. When replace chip, verify the maximum skew between outputs. This will define how good the calibration can be.
  3. Remove the diodes from the output. Will not protect anything.
Layout remarks
  1. Use fmc-adc-100m14b4cha as basis for PCB layout.
  2. Notably have connectors and LED at the same place so can re-use front-panel design and have a uniform look.
  3. Put decoupling C's near FMC connector.

Erik van der Bij - 11 November 2010