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Pablo Alvarez, 2010-12-02 13:56

ReviewFineDelayFMC10112010 improvements

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ReviewFineDelayFMC10112010 Improvements

Schematics layout review held on 10 November 2010

Present: N. Voumard, P. Alvarez Sanchez, M. Cattin, E.van der Bij - CERN

Files used for the review:

New comments (since review on 10 November 2010)
  • Move 125clock to LA_00. Not really important, but it may simplify the data interface. There are not many pins. So probably it is better to leave it where it is. What do you think?
  • What about feeding back the delayed output to the fmc? This would add some jitter, but it could help debugging the card and probably calibrating the fine delays. If you add some resistors you could isolate the feedback in case the added jitter is too high.
  1. "No DRC" crosses on unused inputs and outputs are not systematically placed.
  2. Check the BOM to see if the number of components can be reduced. E.g. no 100uF, R values, package types.
Page 1
  • Switching in the 50 Ohm input termination should not use a jumper as it will not be accessible. Make it programmable via the FMC connector.
    • no free FMC pins left for this purpose
      • It is a requirement! To implement you may use the I/O expander chip that has been used on the carriers: 16-bit I/O Port Expander With Serial Interface MCP23S17-E/ML
  • TRIGSEL should not use a jumper as this will not be accessible. Make it programmable via the FMC connector.
    • no free FMC pins left for this purpose
      • Is a real requirement. See above.
  • The LEDs should not be directly on Trigger_select and termination. Run both from the FMC connector. Use for one would be to show incoming triggers and therefore needs to come from the FMC connector (extended pulse).
    • no free FMC pins left for this purpose.
      • Is a real requirement. See above.
  • Remove note with text "Add termination jumper".
    • done.
  • Move R24A out of page 8, move it to top level, page 1. Otherwise it will be assembled twice.
    • ok, done.
  • Add a note that Vref needs to be 2.5V.
    • OK, but it could be either 2.5 or 3.3
      • In that case, add that may be 2.5V or 3.3V.
Page 2
  1. Drive the VCXO (OSC1) with a DAC, like is used on the SPEC card. This way we can use the board on other carriers and use the White Rabbit tricks.
    • no FMC pins left to connect DAC
      • Is a real requirement. See above.
  • Define the type number of OSC1. Use same as on the SPEC card.
    • it is IVT3205CR 25.0 MHz, same as on the SPEC
  • Pin 36, FPGA_TDC_REF_CLK: add 100 Ohm series resistor as is 3V3 signalling going to 2.5V FMC.
    • done
  • Add 100nF capacitors on +3.3C_PLL. Consider removing the 1nF.
  • Add testpoints on LD, STATUS, REFMON (IC4).
    • OK
  • Cleanup unused pins.
    • OK
  • OUT3, remove wires.
    • done
  • Can pin 63 be left open, or better ground it?
    • it is Self-biased so can be left open
  • Add no DRC marker on unused pins.
    • OK, added, but non-used outputs do not generate ERC errors unless you set the rules to do so.
  • Document design of the loop filter. With the resistors, it is different from the datasheet page 34. Also document the calculation of capacitor values.
    • I copied the values from another design where I used this chip. That time I used ADIsimCLK software to evaluate their values with same conditions (same CLK frequency and IC type)
      • Where do the resistors come from in your previous design? Add note that you used ADIsimCLK and with which parameters.
Page 3
  • Wrong connections of VREF_A_M2C, Gnd, PRSNT_M2C_L: they are on the wrong row (H vs G).* Check G1-G3, H1-3
    • OK, fixed PRSNT is correctly grounded, only these resistors were not needed.
      • DANGER! The signals on row H and G are really inverted between the rows!
  • VREF (H1) should be left unconnected. It is not used.
    • actually it is left unconnected :)
      • See above!
  • PRSNT_M2C_L (H2) should be connected directly to Gnd.
    • it is.
      • See above!
  • Mark that Vref needs to be 2.5V (also on top page, page 1).
    • OK, done
      • Or 3.3V then :-)
  • If need to make available pins, may remove EXT_CLK_P/N as we will use the internal clock in every case.
    • actually, it does not make additional pins since these are gigabit data inputs, not connected to FPGA IO pins.
      it's better to remove this connection.
  • Remove text "Text" below J6A.
    • OK
  • Mark clearly row C, D, G, H (bold below each row)
    • done
  • Put page in landscape so that rows can be put in same order as in VITA specification.
    • done
  • Cleanup DRC markers (some in middle of the line, others missing. Actually not clear which lines are not used.
    • done
  • Grounding of front-panel and standoffs near connector: Replace 1 MOhm by 0 Ohm, remove 22nF. Verify that front-left is connected to stand-off left. Likewise with right side. Is design as is retained on the ADC card.
    • well I copied it from early version of the card above:) DONE.
Page 4
  • Check if double LED used is same as on ADC: DIALIGHT 571-0122-100F (dual 2mm Green LEDs CBI Indicator (with positioning pins).
    • yes, it is.
  • Use same MOS transistor as used for the input termination switch instead of Transistor. Saves a BOM item.
    • sure, done
  • GA0 and GA1 of IC22 are correct. GA1 and GA0 of IC13 need to be swapped?
    • OK, fixed
  • Add note on adressing of the two components.
    • done
  • Add note that TPS3307 is a temperature sensor.
    • actually it is reset circuit. MCP9801 is temp sensor
Page 5
  • Remove inductor L5. I.e. the 3.3V plane will be powered straight from the FMC 3P3V power supply.
    • ok, if U like:)
  • May require rename of all +3.3V to 3P3V. Verify if no +3.3V symbols left.
    • sure, but it's better to name all P3V3 and P3V3_PLL as in SPEC
      • As you like :)
  • Add note about treshold voltages of IC16.
    • done
Page 6
  • The input level is not TTL (as was specified), but is LVTTL.* Now when entering a 5V signal, the diodes will continuously conduct, while not being protected in any way. The fuse will not trigger (or even worse, it maybe even will switch off) and there is no resistor limiting the current.
    • OK, changed to P5V0
  • Can the input fuse handle the bandwidth and short pulses? It is a device made for power use, not signal use. Dependent how it behaves it may heat up and increase resistance dependent on the input signal it receives and therefore may introduce a phase delay. Any experience with this?
    • well, it has fraction of Ohm, I can add small capacitor in series. This fuse is tiny, but will survive 12V connected continuously to the input.
      • We were more worried that it doesn't behave well for high frequencies. Let's pay some additional attention during debug. I added an Issue for this so we don't forget.
  • What is the footprint of the fuse? Can it be replaced by a simple resistor when needed?
    • 2*1.35mm , yes.
  • The inputs of the input multiplexer IC17 TS3usb221 (FET switch) are wrongly connected (signal 1D- can only go to unconnected D- output).*
    • fixed
  • Consider to use a multiplexer with output buffer (the one now used is a FET switch) so that the output level is well defined.
    • this mux has very low rdson and high bandwidth. it easily sopes with 488MHz USB signaling so it will in case of TTL signals
  • The 47 Ohm input termination is in 1206 package and likely is too small to dissipate if a continuous high level is used.* Check the fast ADC card , uses 47 Ohm in 2512 package. See also ADC issue.
    • OK, one could also use 2x 100R 1206 in parallel as they are easier to buy
      • That would be a very nice solution! Can you do the calculation of power dissipation? Indeed on the ADC we needed to handle 10V, so 4 times more power.
  • IC14A is a D-register. The reviewers think a simple buffer would be better. Explain why a register is used here.
    • well, AFAIR there was a discussion about it and I was asked to use register synchronised by same source as output regs so FPGA could easily distinguish in which clock period the input signal came.
      • Pablo: I suggested adding IC3 to register the ouputs from the FPGA to reduce the jitter, but I do not see any use on registering the trigger on the FMC. You can always clock it on the FPGA with the same results.
  • Symbol MC100EPT20DTG (IC5) has the flash in the wrong direction on input pin 7.
    • that's true, I'll ask for correction
  • Symbol 74AC74M (e.g. IC14) has CLR and PR texts rotated and overlapping.
    • fixed, disabled displaying of hidden pins
Page 7
  • Add a note in the schematic explaining the power supply compensation circuit of the TDC-GPX. Notably the supply VDD_TDC is not part of the diagram used in the datasheet and very different from using a Schottky diode. Consider prototyping without the 'compensation' on VDDC_TDC.
    • one can always not mount R17
      well this circuit is result of experience with TDC chip used in CMS experiment for beam position monitor.
      It works fine. One can consult also Mr.Zbig Guzik and Richard Jacobsson for details.
  • Even when the VDDC_TDC supply is 'compensated' like VDDC-H/O, it seems that C22 and R16 are connected to the wrong place and should be connected to the ADJ input of the regulator.
    • fixed
  • Add a note on the nominal voltage of VDD_TDC and VDDC_H/O
    • done
  • Using 100uF as decoupling is overkill. See also the App note Reduced Decoupling where they even reduce the 47uF. The 100uF is not recommended in the datasheet and there are anyway already many 47uF capacitors.
    • as I said I copied working circuit. removed.
  • Suggest to add 100nF decoupling C's like normally is used. On VDD_TDC and VDDC_H/O.
    • I afraid that too low ESR may cause loop stability issues. This solution works fine.
      • I prefer to 'copy and improve' So please add these 100nF, we can always not mount them. It feels weird that it needs 'bad' power to make things work. See also my similar experience with a gbit serialiser.
  • Inputs of TDC-GPX not used correctly.* See table starting at page 11 of the datasheet. Verify all levels as it seems to be critical (some need straight Gnd, others via 10KOhm, even a line with an exclamation mark in the datasheet :-)
    • it seems to be only input power consumption issue. We tied it do ground. Fixed.
      • Not fixed? Where does the 'seem' come from? Please follow the guidelines of the application note. Even if it is only for power consumption, this is an important aspect. If we build 100's of cards that will run 24/24, it may save your electricity consumption that you use at home.
  • E.g. Alutrigger and Tstop5-8 need a 10KOhm to Gnd instead of direct connection.
    • OK
  • StopDis3 should be grounded.
    • OK
  • Tstop5-8 need 10kOhm.
    • OK
  • For readability use similar schematic layout for termination of TDC_STOP as used for TDC_START.
    • done
Page 8, twice
  • Disconnect VBB of all chips.*
    • that's correct
  • May only be used within a single IC (now all VBB's connected together).
    • OK
  • Connect R and S to another level.* VBB is exactly in the middle of Vil and Vih, so not suitable.
    • done
  • Move R24A out of page 8, move it to top level, page 1. Otherwise it will be assembled twice.
    • OK
  • Remove text near R24A ("R24 is optional").
    • OK
Page 9
  • Output is LVTTL. Specification and user requires real TTL drive.* Replace output driver.
    • LVTTL has compatible levels with TTL. 3.3V of output level is within logic High for TTL, but I can switch to AHCT version
      • We want it to drive really with TTL, ie 4.3V to 5V or so. It needs to drive long cables.
  • When replace chip, verify the maximum skew between outputs. This will define how good the calibration can be.
    • SN74AHCT16244DGGR has maximum skew of 1ns
      • But the specication of the board reads: "1 ns resolution or better". So if all our margins are taken here, we may be out of spec. Any ideas for another IC (as otherwise autocal just cannot work good enough)?
  • Remove the diodes from the output. Will not protect anything.
    • what if somebody applies 12V to the output? I think it will.
      • At least connect them to 5V instead of 3.3V now then.
Layout remarks
  • Use fmc-adc-100m14b4cha as basis for PCB layout.
    • this I already did. I will update with newest version.
  • Notably have connectors and LED at the same place so can re-use front-panel design and have a uniform look.
    • I didn't touch the layout
  • Put decoupling C's near FMC connector.
    • OK

  • Erik van der Bij (for review committee) - 11 November 2010
    • Grzegorz Kasprowicz 11 November 2010
      • Erik van der Bij - 12 November 2010