ReviewFineDelayFMC25112010

Schematics layout review held on 25 November 2010

Present: E.van der Bij - CERN

Files used for the review:
http://www.ohwr.org/projects/fmc-delay-1ns-8cha/repository/revisions/13/show/trunk/circuit_board/fmc-delay-1ns-8cha/Schematics
Only the pdf file has been used.


General

  • No comments were given to the latest remarks added since the review on 10 November 2010:
    • Move 125clock to LA_00. Not really important, but it may simplify the data interface. There are not many pins. So probably it is better to leave it where it is. What do you think?
    • What about feeding back the delayed output to the fmc? This would add some jitter, but it could help debugging the card and probably calibrating the fine delays. If you add some resistors you could isolate the feedback in case the added jitter is too high. Indeed I think it would be a great help for debugging and self-test of the card.
  • Check the BOM to see if the number of components can be reduced. E.g. no 100uF, R values, package types. Maybe good to add the current BOM as text file to verify. At least comment if this has been looked at.
Page 1
  • Add a note that Vref needs to be 2.5V.
    • OK, but it could be either 2.5 or 3.3
      • In that case, add that may be 2.5V or 3.3V.
        • done
          • I see only 2.5 mentioned on pages 1 and 3. The 3.3V is not there.
Page 2
  • P3V3_CLEAN of IC18 is not powered anywhere.
  • Confusing name PLL_DAC_SYNC_N for the CS Chip Select signal.
Page 3
  • Pin G1 should be connected to Gnd. Important as is next to EXT_CLK signal.
  • Confusing name PLL_DAC_SYNC_N for the CS Chip Select signal.
  • Mark that Vref needs to be 2.5V (also on top page, page 1).
    • OK, done
      • Or 3.3V then :-)
        • done
          • Not done, only 2.5V mentioned.
  • Put page in landscape so that rows can be put in same order as in VITA specification.
    • done
      • Unfortunately exactly in the reverse order of the VITA spec. May be a source of errors.
      • The project description block is, unlike all other pages, not in the lower right corner.
  • Grounding of front-panel and standoffs near connector: Replace 1 MOhm by 0 Ohm, remove 22nF. Verify that front-left is connected to stand-off left. Likewise with right side. Is design as is retained on the ADC card.
  • TDC_D11 and TDC_D15 have a no DRC check marker, while they should not have (same connections as other signals on this bus).
Page 6
  • The input level is not TTL (as was specified), but is LVTTL. Now when entering a 5V signal, the diodes will continuously conduct, while not being protected in any way. The fuse will not trigger (or even worse, it maybe even will switch off) and there is no resistor limiting the current.
    • OK, changed to P5V0
      • No, the diodes are still connected to P3V3, not to P5V0.
Page 8, twice
  • Move the note referring to VCF and VEF to next to IC7A. It has nothing to do with the MC100EPT23 (I even looked at its datasheet:/).
Page 9
  • When replace (output driver) chip, verify the maximum skew between outputs. This will define how good the calibration can be.
    • SN74AHCT16244DGGR has maximum skew of 1ns
      • But the specification of the board reads: "1 ns resolution or better". So if all our margins are taken here, we may be out of spec. Any ideas for another IC (as otherwise autocal just cannot work good enough)?
        • done FCT series has 0.5ns output skew
          • But in the schematic is the AHCT (SN74AHCT16244DGGR). Which component actually will be mounted? Please make the schematic (and BOM) correspond to the real components that will be mounted.

Erik van der Bij (for review committee) - 25 November 2010