History

Schematics Review

Files for review:

Schematics [pdf]
Altium Designer schematics [SchDoc]
Clocking diagram [pdf]
Configuration and JTAG chain diagram [pdf]
Power supplies diagram [pdf]
Power supplies consumption [pdf]
Bill of Materials [pdf]

Check also the Technical Specifications for more details (still on work)

Schematics review minutes

Date: 02.06.2010 and 03.06.2010
Present: Javier, Erik, Pablo, Tomek, Matthieu

General

  1. Use the same decoupling scheme fro all ICs:
    - 1nF, 0603, NPO, 50V (0.024 euro)
    - 100nF, 0402, X7R, 16V (0.011 euro)
    - 1uF, 0603, X7R, 10V (0.025 euro)
    - 22uF, 1206, X7R, 6.3V (0.34 euros)
    Done (Pablo)
  2. Replace all "0ohm voltage dividers" by 0ohm and 10kohms or 100kohms (to avoid short-cuts on power supplies if both are mounted by mistake).
    Done. Raplaced by 390ohm (Pablo)
  3. Look for resistor network (ladder) for STL terminations.
    To be done by Norbert if necessary (Pablo)
  4. Replace X5R capacitors with X7R.
    Done (Pablo)
  5. Reduce BOM to a minimum.
    Done. New BOM has to be created by Norbert. (Pablo)
  6. Remove some of the decoupling capacitors (around FPGA and GN4124).
    To be done by Norbert if necessary (Pablo)

Power supplies

  1. ICs must get all voltages from the same branch (to avoid start-up issues).
    Done (Pablo). Power supply draft not updated yet
  2. Connect P3V3_FMC to P3V3_PCIe (without regulator).
    Done (Pablo)
  3. Move all voltages generated from P3V3_PCIe to LTM4619 (previously used to generate P3V3_FMC).
    Done (Pablo)
  4. Remove current and voltage measurements, except for P12V_FMC, P3V3_FMC, VADJ and P1V8.
    Done (Pablo)
  5. Move current measurement ICs to the same page as the corresponding regulator (makes schematics clearer).
    Done (Pablo)
  6. Remove ferrites on GN4124 power supplies, except for VTT_AB, VTT_CD and VDDAUX.
    Done (Pablo)
  7. Remove ferrites on digital power supplies of the DDS (DVDD_P1V8 and DVDD_P3V3).
    Done. Analogue supplies are now connected to the standard P3V3 through a ferrite. (Pablo)
  8. Add 100nF decoupling capacitors all around the FMC connector.
    Done (Pablo)
  9. Remove multiple names on the same voltage rail.
    Done (Pablo)
  10. Remove P3V_OSC power supply.
    Done (Pablo)
  11. Remove ferrites on OSC1.
    Done (Pablo)
  12. Connect 100kohm resistors (on the output of OSC1) to P3V3_CLEAN_PLLEXT.
    This resistors have been finally removed (Pablo)
  13. Remove 10kohms resistors in parallel on P1V5 (GN4124 page).
  14. Merge P1V2_FPGA_CORE and P1V2_MGT.
    Done (Pablo)
  15. Merge P3V3_CLEAN_PLL125 and P3V3_CLEAN_PLLEXT.
    Done (Pablo)
  16. If P5V is not used by the FMC, it can be reduced to 3.5V to reduce power dissipation of linear regulators.
  17. Add a pull-down resistor on SET pin of OSC5, to be able to enable spread spectrum modulation.
    Done (Pablo)

Gennum

  1. See mailing list archive for Tim's comments (Thread: PCIe carrier schematics review).
  2. Check if it is possible to remove the serial 22ohms resistors on P2L data lines.

Clocking

  1. Replace TCXO for the GN4124 by a crystal.
    To be done... (Pablo)
  2. Replace ac-coupling capacitors on GTP clk. ref. with higher values (10nF or so).
    Done (Pablo)
  3. Check TCXO datasheet, to see if ac-coupling + bias is needed.
  4. Replace 0.1% 100kohms resistors used on OSC1 and OSC2 output with standard 1%.
    Done (Pablo)
  5. Try to find a 3.3V LVDS buffer and remove the 2.5V regulator. Or change the regulator type to use the same as other voltages.
    Done (Pablo)
  6. Configure pin swapping on eSATA connectors.
    To be done.. (Pablo)

DDR3

  1. Data lines swapping is possible, with some constraints (-> Tom?).
    Not explained yet to Norbert (Pablo)
  2. Remove comment on DDR termination placement.
    To be done (Pablo)
  3. Check if R84 is needed.
    To be done (Pablo)

FPGA

  1. Replace R17 by 100kohms.
    Not replaced. R17 to 0ohms and R14 to 5k1ohms. There should not be any risk of shortcut. (Pablo)
  2. Check FPGA symbol (ask DEM how they create such symbols).

FMC

  1. Connect TRST_TO_FMC to the IO expander.
    Done (Pablo)
  2. Replace 0603 0ohm resistors for power supplies on HPC rows by 0402.
    Done (Pablo)

Voltage translation buffers

  1. Look for smaller package.
    To be done (Pablo)
  2. Configure pin swapping.
    To be done (Pablo)

PLLs

  1. Check PLL filter component values -> take the same as the WR switch.

SFP

  1. Check RD and TD on the SFP symbol.
    Checked. Same pinout as in Xilinx dev kit sp605 (Pablo)

Misc

  1. Check MCP23S17 (IO expander) exposed PAD connection.
    To be done (Pablo)
  2. Change all pages to A3.
    To be done (Pablo)
  3. Check title boxes.
    To be done (Pablo)
  4. Typo in the comment on the left of FMC connector page -> imped_e_nce.
    To be done (Pablo)
  5. Remove net names on PGOOD pins (to avoid compilation error and confusion), keep the pull-up for debug.
    To be done (Pablo)