FMC Analog to Digital Converter developments
CERN's user needs are compared to define the specifications of the ADC cards to be developed. Main input is coming from Stephane Deghaye.
Specification
**FmcAdc100M14b4cha ** | FmcAdc100M14b4chb | FmcAdc100M14b2cha | FmcAdc100k16b8cha | FmcAdc100k16b2cha | |
---|---|---|---|---|---|
4-channel, progr. gain | 4-channel, progr. offset | 2-channel, progr. gain&offset | 8-channel, progr. offset | 4-channel, progr. gain&offset | |
jumper settable gain | autocal (offset, gain) | jumper settable gain | autocal (offset, gain) | ||
Project aborted | On-going. 3 protos built (June 2010) | Not started | Started reviewing specs (June 2010) | Not started | |
Parameter | Value | Value | Value | Value | Value |
max. sample rate | 105 MSPS | 105 MSPS | 105 MSPS | 100 kSPS | 100 kSPS |
bits/sample (raw) | 14 bit | 14 bit | 14 bit | 16 bit | 16 bit |
bits/sample (effective) | |||||
channels | 4 | 4 | 2 | 8 | 4 |
analog bandwidth | 25 MHz | 25 MHz | 25 MHz | 25 kHz | 25 kHz |
Input impedance | 50 Ohm | 50 Ohm/ 10 KOhm jumper selectable | 50 Ohm/ 10 KOhm jumper selectable | 50 Ohm/ 10 KOhm jumper selectable | 50 Ohm/ 10 KOhm jumper selectable |
Offset adjustment | not possible | +/- 10V ? | +/- 10V ? | +/- 10V ? | +/- 10V ? |
Offset step size | |||||
min. input voltage range | +/- 40 mV for full scale | +/- 0.1V | +/- 40 mV for full scale | +/- 0.1V | +/- 40 mV for full scale |
max. input voltage range | +/- 10.24 V for full scale | +/- 10 V for full scale | +/- 10V for full scale | +/- 10 V for full scale | +/- 10V for full scale |
gain steps | 1,2,4...256 | +/- 0.1V, 1V, 10V jumper selectable | 1, 2, (4), 5, (8) | +/- 0.1V, 1V, 10V jumper selectable | 1, 2, (4), 5, (8) |
max. gain error | +/- 8.5% | +/- 2% | +/- 2% | +/- 2% | +/- 2% |
max. input voltage offset | max. 15 mV | ||||
Calibration | manual 0V | manual 0V | autocal (offset, gain), or only manual 0V | manual 0V | autocal (offset, gain), or only manual 0V |
External trigger | TTL (0.7V) | TTL (0.7V) | TTL (0.7V) | TTL (0.7V) | |
External clock | via FMC carrier | via FMC carrier | via FMC carrier | via FMC carrier | |
Connectivity | FMC/FMA/MMCX? | FMC/FMA/MMCX? | Fanout cable | FMC/FMA/MMCX? | |
SNR | |||||
Crosstalk | |||||
Notes | Cancelled development | Should be able to replace SIS modules | Priorities: 1) input impedance programmable, 2) autocal, 3) offset autocal, 4) gain autocal |
Notes |
---|
Would be nice if SW could detect jumper settings. |
Would Stephane need a sweeping (unstable) clock? This would not be possible to implement with serial ADC |
> -----Original Message-----
> From: Stephane Deghaye
> Sent: Thursday 03 December 2009 17:36
> To: Erik Van Der Bij; Maciej Fimiarz; Javier Serrano
> Subject: RE: FMC ADC OHR page
>
> Without meeting:
>
> The offset could dependent on the full-scale (this is the
> usual case). However, if that can be done easily, a offset
> bigger than the full-scale is very convenient. Remember the
> example of the signal where the operation is interested by
> the full shape and the crest value. The bigger offset allows
> us to use a small full-scale (e.g. 1V) and still move the
> acquisition window on the top of the signal (e.g. +9V).
>
> I'll try to find out:
> - Typical full-scale (need to have a look at the global
> configurations)
> - Typical offset
> - Typical values of RF signals (not LLRF), CVORB/G, GFAS, PO
> (pulsed converters), kickers...
> - Typical sweep for external sampling frequencies (e.g. 96
> MHz in CTF).
>
> Cheers,
> Stephane
Status
- 04-06-2010 - FmcAdc100M14b4cha: 100 MSPS, 14 bits, 4 channel proto built. FmcAdc100k16b8cha checking specs for feasibility.
- 19-03-2010 - FmcAdc100M14b4cha: 100 MSPS, 14 bits, 4 channel under design.
- 30-11-2009 - FmcAdc100M14b4cha had too much SNR. Rethink user needs (e.g. programmable offset instead of programmable gain
- 2-12-2009 - Meeting with S. Deghaye on needs for ACCOR
-- ErikVanDerBij - 4 June 2010