FMC Projects » VME FMC Carrier (VFC)

After the recommended changes from the design review were made, twenty PCBs will be built. First only ten of them will be assembled. Preliminary tests will decide if the other ten will be assembled later.

The layout of the V2 is ready. The schematics and PCB design will be reviewed by a team of at least 4 people. The changes are the result of many tests done before and the design review held in August. The new design will also be easier to produce.

Four designers have reviewed the schematics design of the V2 of the VFC card. The suggested changes will be integrated and will improve the design and manufacturability. By the end of August a new layout will be made.

The schematics have been updated to cover most of the issues found during the sprint. We will hold a review in the coming week.

Since the Scrum sprint to quickly debug the design with four engineers, already fourteen hardware problems have been found. Many are small bugs, but it also has been found that the SFP serial inputs are not usable as the Tx and Rx part are swapped.

We are using the Issues feature of the Open Hardware site to keep track of all issues and make sure that they will be handled in future versions of the design.

As the project is going slower than we want, we decided to start a sprint to debug the hardware design. For two to three weeks four engineers will be intensively working on testing and debugging the design. We follow the scrum methodology, meeting shortly every morning to decide on what work needs to be done on that day. The aim is to test the current design as quickly as possible and to collect info for the next version of the design.

To allow other people to start developments for the VFC card, ten additional boards have been produced. During the assembly, problems with the FMC connectors appeared that could be circumvented by using a thicker stencil (that will apply more solder) and then reworking some capacitors manually. For new productions the layout will need to be modified to allow more spacing between these capacitors. At the same time the JTAG chain that programs the two FPGAs will be split into two seperate chains as there have been some programming problems. The modification work on the layout will start in two or three weeks time.

Currently there are four boards working while an additional eight boards need rework.

The pll access have been tested. It is working and the PLLs have been configured to work at a few frequencies(66.6, 100, 200, 400MHz).

Voltage monitoring ADC tested: ok

The VADJ control has been tested. It is possible to set using the digital potentiometer between 1.2V and 3.3V