VME FMC carrier¶

Project Status: BreakDown¶

Main Features¶

• 2 Spartan6 FPGA
  • One dedicated to system tasks (S-FPGA)
  • One fully available for the user applications (A-FPGA)
• 2 LPC (Low Pin Count) FMC slots
• 40 user defined single ended (20 LVDS) connections from the A-FPGA to P2 available for rear plug-in units (transition modules)
• flexible clocking resources
  • 1 Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO)
  • 1 any rate I2C programmable crystal oscillator
  • 1 Direct Digital Synthesizer (DDS)
  • 3 Phase Locked Loop (PLL) chips for clock cleaning and redistribution to the FPGAs and the pluggable modules
• Large amount of on board memory
  • 2 completely independent 72Mbit ZBT SRAMS
  • A 2Gbit DDR3
  • 2 SPI 128Mbit flash proms for multiboot S-FPGA powerup configuration, storage of the A-FPGA firmware or of critical data
• Front panel connectivity
  • 2 Small Formfactor Pluggable (SFP)
  • 4 lemos configurable in all possible input/output combinations
  • 1 e-SATA (only in non-VME applications)
• 12 layer printed circuit board

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Documentation¶

Functional specifications¶

• Approved document: source:/trunk/documentation/specifications/VFC_FunctionalSpecifications.pdf

Technical specifications¶

• Official design data EDMS EDA-02030
• LHC equipment name: CVORK
  • Controls Configuration Database entry
  • Controls EDMS page
• schematic diagram: source:/trunk/circuit_board/VmeFmcCarrier.pdf
• overview presentation: source:/trunk/documentation/specifications/VFC_technicalSpecificationsOverview.pdf
• bill of material: http://www.ohwr.org/attachments/download/113/BOM.xls
• Manufacturing test suite

Users¶

• List of (potential) users of the VFC

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Status¶

Date	Event
03-08-2009	Functional specification written.
24-03-2010	PCB layout started
10-05-2010	Vadj fixed to 2.5V for FMC slot 2 to solve problems with bank power supplies.
11-05-2010	All active components ordered.
23-06-2010	Layout files received and being reviewed.
05-07-2010	PCB layout review held.
09-08-2010	PCB layout good for production.
01-09-2010	Simulation started. Many troubles getting connectivity files out of schematics. Redo by hand.
15-09-2010	PCB being produced at CERN. Expect assembled boards by mid October.
06-10-2010	Two PCB's being assembled. A third one will come later.
15-10-2010	Problem with solder mask for 0402 capacitors under BGA detected. PCB specification will be changed.
19-10-2010	1st prototype received, waiting for the front panel.
08-11-2010	1st prototype powered: 3 DC/DC are not working.
09-11-2010	2nd and 3rd prototype received: one powered and no issues on the PS this time
17-12-2010	Test code loaded in the System FPGA and PROM programmed. JTAG and PROM loading are working. VME access OK.
11-04-2011	Ten additional boards produced. Two reworked and work, but have JTAG issues. Eight still need rework.
11-04-2011	Modifications to layout required. Can start in two to three weeks time.
07-06-2011	Start of sprint to debug the hardware design. 4 engineers intensively working on it, following the scrum methodology.
24-06-2011	End of sprint to debug hardware design. Uncovered 18 Issues. DDR3 memory and DDS not debugged yet.
10-08-2011	New version of schematics ready.
16-08-2011	Schematics design review held review16082011. The design office will layout from 24 August on.
13-09-2011	Schematics still being updated. The design office will layout from 19 September on.
06-10-2011	V2 layout ready. Needs schematics and PCB review.
18-10-2011	V2 schematics and PCB review held.
25-10-2011	Will produce 20 PCBs. First only 10 will be assembled.
15-11-2011	Expect assembled boards by mid- December January.
22-02-2012	Ten assembled boards received. Needs patch on power plane. JTAG, VME and FPGA config work.

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Andrea Boccardi, Erik van der Bij - 24 February 2012