Schematics design review of the VME FMC Carrier (VFC) to go from V1 to V2.

Date: 16 August 2011
Present: Andrea Boccardi; Matthieu Cattin; Erik Van Der Bij; Tomasz Wlostowski

Below some of the review comments that were sent before the meeting can be found. During the review these and other issues were discussed to be included in the V2 of the design.

Andrea published a short pdf file with the main comments: ReviewMinutes.pdf

The design office can start working on a new layout from 24 August on.

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From: Erik Van Der Bij
Sent: 15 August 2011 17:33
To: Andrea Boccardi
Cc: Tomasz Wlostowski; Matthieu Cattin; Pablo Alvarez Sanchez
Subject: VFC design review

Hi Andrea,

Please find below my review comments.

Best regards,
Erik


TECHNICAL

Page 10: SFP powering is different from SPEC. Eg. VccT has only 100 nF, while the SPEC has 100nF//22uF.

Page 10: CF1/CF2 capacitor: should be X7R and "The insulation resistance of the 0.47 ?F capacitor
should be greater than 300 M?." Verify if selected capacitor has this high isolation and is correctly
specified in BOM.
Currently the BOM specifies for 470nF X5R: GENERIC CC0402_470NF_6.3V_10%_X5R The SPEC card only
uses X7R type of capacitors.
For comparison: AVX X5R: 10,000M? or 500M? - ?F, X7R: 100,000M? or 1000M? - ?F

Page 10: Thradj does not need a capacitor Page 10: Thradj: how is value of 10KOhm chosen? The
datasheet doesn't seem to specify a value.

Page 10: lines like WR_TXFault, WR_MODDEF[2:0] and WR_LOS don't have a pull-up. The SPEC card
does.

BOM, industrialisation.
- reduce the number of resistor types. 28 different values used, of which 14 values are used only 1,2 or 3
times and 4 other values are used 4 times only. If needed, use resistors in series or parallel. (cf SPEC: 9
values in total).
-reduce number of capacitor values. 15 types (cf. SPEC: 8 types)

GRAPHICAL

Page 4 and others: Not Mounted components are marked graphically by dotted lines around them. In
the SPEC we use a parameter ("No") attached to each component so that BOM can be automatically be
generated.

Page 10: symbol of SFP has note in red: "Wrong direction of the signal on the symbol". Should ask design
office to change this. On SPEC the arrows on the symbol are not shown.

Remove 'dots' from references and symbols (setting in Altium)

Typo in filename of page FrontPannel.SchDoc -> FrontPanel.SchDoc

Page 2 and 4: specify value or range for Vadj1 and Vadj2.

LICENCE INFO ON SCHEMATICS

Add OHR licence text on each page.
See http://www.ohwr.org/documents/88 -> Howto doc:
Copyright CERN 2011.
This documentation describes Open Hardware and is licensed under the CERN OHL v. 1.1.
You may redistribute and modify this documentation under the terms of the CERN OHL v.1.1.
(http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A
PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for applicable Conditions



From: Pablo Alvarez Sanchez
Sent: 15 August 2011 18:05
To: Erik Van Der Bij; Andrea Boccardi
Cc: Tomasz Wlostowski; Matthieu Cattin
Subject: RE: VFC design review

Hi,

Here you have mine:

  • CDR Data and CDR CLK use could be simplified if conected to the same half block.
  • Probably the use of a parallel configuration bus between system fpga and application fpga is not
    justified. Notice that the configuration is read from a serial prom already. So, in theory a serial slave bus
    could be enough and would save some IOs. These free IOs can be useful to route the remaining pairs of
    FMC 2 that are not routed (LA32 and LA31)
    *LA0 and LA1 for FMC1 should be routed to GLCK16 to GCLK 12 to simplify synchronous source clocking
    (see http://www.ohwr.org/attachments/246/ClockingFMCs.pdf)
    *LA14 on FMC2 should be moved to the opposite half bank.
    *The FMC M2C clocks could be connected to BANK3 or BANK1. TBDiscussed *VMEP0_TCLK and
    VMEP0_BUNCHCLK cannot use global clock resources simultanously.
    *SYSAPP_CLK is really necessary? One could connect one of the M2C clocks here.
    *PLLFMCX_2AFPGA clocks are really necessary? They could be replaced by the M2C clocks...
  • The BWX lines to the SRAMS are really needed? If not one could remove them and gain some place for
    the M2C clock on bank 1 and bank3.
    *It would be good to add an _N to the active low signals where needed. (VME control signals mainly)

Cheers

pablo



From: Tomasz Wlostowski
Sent: 15 August 2011 18:27
To: Pablo Alvarez Sanchez
Cc: Erik Van Der Bij; Andrea Boccardi; Matthieu Cattin
Subject: Re: VFC design review

Hi,

Here are my comments:

Power Supplies.SchDoc
------
- replace PTH04T230WAZ with WAD version (soldering problems)
- didn't we plan to get rid of the negative power supplies?

AFPGA.SchDoc
------

- There are only 4.7uF decopuling caps on most power rails. Is this enough? (also how about their
reliability?)
- Swapping MGT101 with MGT245 would simplify the design of the inter-fpga link (limitations of Xilinx's
clock distribution)

SFPGA.SchDoc
------

- SFP2 GTP transceiver deserves an independent reference clock.
- Inter-FPGA link: GBIT34_REFCLK isn't absolutely necessary (All inter-fpga links are in the same GTP row,
so they can share a single clock input). IMHO GBIT34_REFCLK could be better used for delivering the
clock for the SFP2 or SATA transceiver.
- R42 should not be mounted by default
- VMEH22501 buffer next to J1 - passing the TDI-TDO connection between the two FPGAs will only
increase the JTAG complexity on the PCB (and may cause even more SI problems). I would recommend
replacing the VMEH buffer with something slower (for example LV245 or even HCT245).
- Do we need so many PCB revision jumpers?
- (BOM) Why 220n caps for decoupling the GTP supply while using 100n everywhere else (as Erik pointed
out - the BOM could be optimized)

Clock Generation.SchDoc
-------
- PLL in IC6 is useless (is this deliberate?)
- IC3 has no output filter (nor a cleaning PLL). The quality of the DDS clock output will be very bad.
Consider using a DDS-PLL combo.
- IC18 won't work with a 25 MHz reference (loop filter cutoff freq is 40 MHz).
- IC18/12 - I'd recommend reducing the filter bandwidth (AD9516 produces very low phase noise above
~20kHz offset)
- (right side) C40, C38, etc. - 100pF looks a bit too small for these coupling caps (|Z| = 16 ohm @ 100
MHz)

FrontPannel.SchDoc
------
- LEMO termination resistors should have at least 0.5 W total power rating (to withstand a TTL load over
50 Ohm)
- Consider using the same symbol for the SFP as in the SPEC. The cages/connectors are compatible.
- replace 100p coupling caps on the WR lanes with 10n caps
- L5, L6, etc. - ferrite beads should be good enough here
- "They share 1 pad" - they don't have to, placing these caps close to each other is also OK.
- missing pullups/pulldowns on SFP control lines (see SPEC schematics)

  • Probably the use of a parallel configuration bus between system fpga
    and application fpga is not justified. Notice that the configuration
    is read from a serial prom already. So, in theory a serial slave bus
    could be enough and would save some IOs. These free IOs can be useful
    to route the remaining pairs of FMC 2 that are not routed (LA32 and
    LA31)

Pablo's right - using a parallel config bus won't give any speedup (because the config speed is limited by
the speed of the VME. Loading a
1.5 MB bitstream over Xilinx's serial bus on the SPEC is just 0.5 seconds.

Cheers,
Tom


Erik van der Bij - 16 August 2011

ReviewMinutes.pdf (75.2 kB) Erik van der Bij, 2011-08-17 12:13