Overview
This project defines an area of common registers inside FPGAs, which allows for unambiguous identification of the FPGA bitstream and automatic probing of internal Wishbone cores by external software.
- Status: Planning
Latest news
Initial Draft of Specifications
The initial draft of the specifications for the FPGA configuration space has been released.
Members
Manager: Alessandro Rubini, Manohar Vanga
Developer: Alessandro Rubini, Juan David González Cobas