HDL Core Lib » Gennum GN4124 core

CERN has adapted for its particular applications the original GN4124 VHDL and Verilog examples from Gennum. Alan Hutton, Gennum director of Global Distribution Sales & Marketing, has given CERN the green light to publish this modified code as open source.
Gennum just likes the references to Gennum be removed from the original code. Of course Gennum cannot support this modified code, but they will have their usual support and Tim Fairfield's blog

CERN's PFC card and the Gennum to Wishbone core is featured on Gennum's GN4124 Design blog

The Gennum core has been tested on the SPEC and the PFC boards.
Both CSR and DMA wishbone interfaces works well.

The beta version has been tested on a Gullwing development board from Gennum.
For testing purpose, one 8KB RAM is connected as a slave on the DMA wishbone.
Two slaves are connected to the CSR wishbone. One contains four status registers, three with fixed values and one with the state of the on-board DEBUG switches. The other slave have four control registers and one of them is controlling the on-board LEDs.

The beta revision has been tagged in SVN http://svn.ohwr.org/gn4124-core/tags/revision-beta/

A first bi-directional DMA transfer has been achieved on the Gullwing development board.
The interrupt message generation (MSI) is also working fine.