HDL Core Lib

This new version includes a pipelined mode to cater for devices with high throughput and high latency such as DDR RAM chips. See the draft in Wishbone B4 Specification.

Wishbone slave core generator (wbgen2) is a Lua script for generating VHDL Wishbone slave cores from a register set description provided by the user. By the ”slave core” we mean a HDL entity which is connected to Wishbone bus on one side, and on the other side it provides ports for accessing memory mapped registers, FIFOs and RAMs. More info here.