This project covers the development of re-usable HDL cores for FPGAs, each of which is a separate sub-project (see complete list). Although there are no strict rules on practices, there is an emerging coherency developing around the concept of Wishbone-based design. We collaborated in the update of the Wishbone B4 Specification to include a pipelined mode which enhances communication with high-latency high-throughput devices, such as DDR RAM controllers. Another important development is the Wishbone slave generator, which helps in the repetitive task of creating Wishbone slaves in VHDL and Verilog. For VHDL development, please use the VHDL coding guidelines.