Overview

The LatticeMico32 processor is a Verilog core for a 6-stage pipelined RISC architecture. Originally designed for Lattice FPGAs, this project modifies it to support Altera and Xilinx. It has GNU toolchain support since gcc 4.5. This code is a fork of the milkymist fork of the original LM32 design.

Noteworthy features:
Harvard architecture for memory/instruction Wishbone buses (v4 in this port)
Single cycle issue for most instructions (including multiplication)
Debug/gdb support via JTAG or embedded OS (including single-stepping)
Optional instruction and data caches (1- or 2-way associative)

Most features can be disabled to fit it into 1500 Cyclone3 LUTs. A full system (debugging, all instructions, data and instruction cache) costs 2500 LUTs.

Timings:
On Cyclone3 it reaches 125MHz
On Arria2 it reaches 175Mz

  • Status: Beta

Issue tracking

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Members

Manager: Wesley W. Terpstra
Developer: Marcus Zweig, Mathias Kreider