CernFIP » nanoFIP Test Board

20 NFTC boards pre-validated at HLP have been received and are now being tested

Two V2 test boards were received by HLP on Tuesday 15th March.
HLP validated them and shipped one board to CERN; it was received on Friday March 18th.
At CERN the test board has been tested in memory loopback mode, 124 bytes, 5ms macrocycle and has performed more than 42.800.000 sucessful cycles during the weekend 19-20 March.
It is considered therefore validated and the green light to the production of the remaining 18 boards is already given!

Twenty NanoFIP test boards are ordered. These boards will be an improved version of the prototype that is working since July 2010. This version has more test points and can also be used to test the foreseen JTAG programming extension of the NanoFIP. We expect the new boards by the end of March so that they will be ready for the tests under radiation in May 2011.

The production and consumption of variables is working and has been tested for over two days. The data is not yet checked continuously, we're waiting for an extension of the firmware of the NanoFIP test board that allows the NanoFIP to resend the data it has received.

See http://lists.ohwr.org/sympa/arc/nanofip-test-board/2010-08/msg00000.html

The test board and the software has been validated. It is now ready to accept the first version of the NanoFIP code to start testing the WorldFIP functionality.

The assembly of the boards started and the firmware development is progressing. A Draft software manual is available with screenshots that give a good impression of the look-and-feel.

The PCB layout has been verified and is OK. The PCB boards and all components are ordered and will arrive end of June at the company. As next step the firmware will be written. For this a version of the firmware specification has been written and has been verified by CERN.

We received a new layout that should include changes requested after the PCB layout review. It will be verified before launching the production of the prototypes.

The PCB layout review has held. It revealed several issues that will make the design more robust and that will improve its documentation. As there are major corrections to be done, another review will be needed before the PCB may be produced.