WP10 Implementation of a JTAG Master Controller for the reprogramming of the "User-FPGA"
Description
Regarding the extension of the project with the implementation of a JTAG Programming Master controller, the work package 10 includes the
- extension of nanoFIP's functional specification
- VHDL implementation of the Controller
- testing with VHDL simulations
- Bus Arbiter software developments
- testing on real hardware
In collaboration with CERN, TE-EPC, the deliverables are
- Updated nanoFIP functional Specification
- VHDL code that implements a JTAG Master Controller
- VHDL test bench that tests the JTAG Master Controller
- Bus Arbiter software
- Testbed
The estimated duration is four person-months
Date | Status |
---|---|
05-2011 | Project startup |
06-2011 | Software developments by S.Page; Hardware developments by E.Gousiou; Simulation Test Bench by G.Penacoba; S.Page spotted lib(X)SVF, under ISC, which will be used |
07-2011 | Testing phase; project [presentation](Presentation-of-JTAG-feature |
08-2011 | Stable version since Jul 29; Testing over time |
Useful documentation
- Updated specs
- JTAG feature implementation
- JTAG Controller for nanoFIP: Functional Requirements
- Presentation on the JTAG feature
Acknowledgments
Warm acknowledgments to Clifford Wolf for lib(X)SVF :)