Summary of discussions in the foss-pcb mailing list

This is a place holder to keep track of ideas discussed in the foss-pcb mailing list, which aims at defining a roadmap to bring FOSS PCB design tools to a level of quality and features comparable with some of their non-open counterparts.

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Phase I. The Features.

Below is a list of desirable features for a FOSS PCB design tool, as discussed in the mailing list.

  • Cross platform support.
  • Procedure to accurately transfer schematics and PCB layout to and from other ECAD tools (guaranteed supportable for other FOSS tools; proprietary tools if possible). Extra points for true reversability.
  • IPC-356 netlist export, which is used by board fab houses to drive their flying probe electrical test equipment.
  • Integrated push-and-shove router (or at least push/walkaround mode).
  • Hardware-accelerated display engine.
  • Support for split planes. You can draw the planes in negative (i.e. you draw only the cuts in a contiguous copper plane and assign the resulting slices to power supply nets).
  • Object filtering. For example, typing "obj.type==Track && obj.layer==Top" selects/masks/unmasks all tracks on the top layer.
  • Property editor capable of editing groups of objects of different types (a nice tabular view).
  • Assigning footprints directly on the schematic. Library browser in a docker window with footprint/symbol viewer.
  • Scriptable constraint editor. There are constraint categories, like Length, Width, Clearance where the user can specify the acceptable values and also the conditions (using the scripting language) under which the constraint is checked.
  • Common shell for schematic editor and PCB layout applications. One advantage of the common shell is allowing a component selected in the schematics to be highlighted in the layout, and viceversa.
  • Pin-swapping and back-annotating pinswap data from the PCB to the schematic (without any messing with netlists).
  • Integrated functional simulation (ngspice, Qucs...). "A simulation run should be as simple as with ltspice."
  • "Slightly integrated" EM simulation (for power/gnd integrity, crosstalk...).
  • A library model that contains all the complex relations between symbols, footprints, purchase information, simulation models and comments.
  • Export/import to a 3D mechanical CAD application.
  • Web-based model for parts libraries using revision control to leverage crowd sourcing.
  • Designs in human-readable text format so text diffs can be used to efficiently track changes using version control systems. Extra points for preserving file content order so the diffs are minimal and easier to interpret. Extra points for visual diff-ing involving reasonable development effort.
  • Pin swapping constraints, i.e. a possibility to attach a script to a particular component which governs which pins can be swapped and how. For example in Xilinx FPGAs, such a script would detect the supply nets for each bank and automatically add the corresponding I/O pins to an appropriate swap group. It could also identify half-banks (a nightmare when using IOSERDES blocks in Spartan/Virtex6, etc...) or GTP clock regions.
  • Automatic pin assignment file generation for ISE/Quartus/Lattice from the schematic.
  • Align/distribute tool in PCB layout editor.
  • From the mailing list: "To refine this idea a bit, perhaps what we really need is a cross-platform, "cross-ecosystem" tool for generating schematic symbols and PCB footprints, that could import from those three, and export to those three as well. That could be a phenomenal "rosetta stone" application, and could do wonders for the OSHW community as a whole."

Phase II. Choosing a tool to start with.

The list above represents a state-of-the-art PCB design tool. We have decided to work on Kicad and try to bring it to a level of quality and features compatible with the list. We think Kicad is the current FOSS project which most resembles what we have in mind as our future PCB design tool, and we feel more capable of making meaningful contributions to it than to other tools. See the project we have created to organize our contribution to Kicad.

Phase III. Coming up with a list of work package descriptions.


kicad_wp.pdf (217.3 kB) Javier Serrano, 23/04/2012 15:58