Version 86 (Javier Serrano, 10/11/2011 21:53)

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h1. Agenda for the Open Hardware Workshop
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This workshop will be held during the Sunday preceding "ICALEPCS 2011":http://icalepcs2011.esrf.eu/, i.e. 9 October 2011 in Grenoble, France. There will be a participation fee of 50 euros to book the "venue":http://www.congres-wtcgrenoble.com/makalu.htm. This fee includes a pack lunch. You will find the current state of the program below. Please subscribe to the "workshop mailing list":http://lists.ohwr.org/sympa/info/oh-workshop-2011 if you wish to take part in the discussion. If you want to participate in the workshop, please use the "official registration page":http://icalepcs2011.esrf.eu/registration (notice it is certainly possible to attend only the workshop instead of workshop+conference, by using "this link":http://icalepcs2011.insight-outside.fr/Visitors/index.php?onglet=4&idUser=&emailUser=). The deadline for registration is Friday 30 September 2011.
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h2. Morning
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* Session 1: Introduction and legal framework. This will be an opportunity to define exactly what we mean by OH and discuss the latest developments on the legal side, such as the recently-published CERN Open Hardware License.
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** *09:00-09:30 Open Hardware: what, why, how, when, who* (Javier Serrano, video CC BY-SA).
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** *09-30-09:40 Summary of the "Open Hardware Summit":http://www.openhardwaresummit.org/* (Tomasz Wlostowski, video CC BY-SA).
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** *09:40-10:00 Open Hardware Licensing* (Myriam Ayass, video CC BY-SA). The CERN Open Hardware Licence v.1.1 was released on July 7 2011. The purpose of this presentation is to provide some background information as to the context in which it was developed, the reasons and rationale for developing it and expected outcomes. A description of the main provisions will be given together with the main issues and solutions that were discussed during the process. Furthermore, thanks to the feedback received from the community, plans for v.1.2 of the licence will be presented.
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** *10:00-10:30 Arduino* (David Cuartielles).
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** *Discussion*.
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* Coffee (10:30-11:00)
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* Session 2: Business models. It is very interesting to discuss the role(s) of companies and how they can make business under an open paradigm.
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** *Open Hardware in Creotech* (Grzegorz Kasprowicz).
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** *Open Hardware perspectives in National Instruments* (Ravi Marawar, 20 min). National Instruments (NI) is a Commercial-off-the-Shelf (COTS) system provider that combines heavily researched designs manufactured with state-of-the-art quality control processes and guaranteed long term lifecycle management. NI product designs are influenced by reliability and quality goals, calibration needs, safety certifications, environmental and security  compliance requirements and longevity expectations. A significant attention is given in the design process to ensure compatibility and ease of use of various NI and third party products that are likely to be integrated into a system. This talk will share NI perspective of combining these factors with OHWR designs embedded with domain expertise.  NI believes this will lead to  excellence in comprehensive design and commercial grade products that will benefit entire industry from a technical and financial point of view. 
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** *First experience in Seven Solutions* (Eduardo Ros, 20 min, video CC BY-SA). "Seven Solutions":www.sevensols.com is a technology based company (intensively engineering based company). The company offers services of design, technology consulting, custom electronics, embedded computing, etc.  After launching its own hardware based products, Seven Solutions is aware of how the OHR paradigm can benefit SMEs in this field, by providing a shield of confidence (making SMEs dependable entities), facilitating the active participation in medium scale designs as part of an engineering community and making easier the process of how an SME offers its services as add-ons on projects conjointly run by different institutions. Furthermore, OHR allows development cost sharing among different institutions since Intellectual property does not create borders between participating companies.
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** *Clear roadmap for Open HW in Instrumentation Technologies* (Borut Repič, 20 min, video CC BY-SA).
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** *The Facebook Open Compute Project* (John Kenevey, 40 min, video CC BY-SA). Facebook's Open Compute Project is a nascent community which is actively seeking participants who are passionate about making strong technical contributions to defining and delivering the most efficient server, storage and data center designs. One of the enablers of said community is to ensure they have the necessary tools to provide open electrical and mechanical designs to the Open Compute Project.  I will share Open Computes genesis and future community driven trajectory in this presentation.
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** *Discussion*.
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* Lunch (12:30-13:30)
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h2. Afternoon
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* Session 3: Tools. Most of our tools are not open themselves yet. Here we can discuss about what is the current offer and possible future plans. This affects mainly HDL simulation and PCB design.
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** *Makefile-driven HDL* flow (Pawel Szostek, 15 min, video CC BY-SA). Maintaining HDL is a source of many problems, not necessarily related to design issues. When developers want to perform a synthesis, they have to struggle through massive clicking job in an IDE and face compatibility problems among different versions of the same tool. What is more, synthesis of big projects is a time and resource-consuming process that makes the edit-compile-test cycle unreasonably long and makes it harder to introduce trivial modification to the hardware. When simulating VHDL models developers usualy have to set correct compilation order. Hdlmake is a kind of swiss-army knife that tries to solve mentioned problems by generating a multi-purpose makefile. Hdlmake automatically detects file dependencies, generates IDE-specific project files, facilitates remote synthesis. It also offers a solution that makes modularization and managing of a project easier.
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** *Icarus Verilog/VHDL* (Pawel Szostek, 10 min, video CC BY-SA). In the era of open source many companies and institutes are in the process of streamlining their hardware design flow to adopt open software development tools which will facilitate collaboration with external actors. We aim to build an open source tool that would allow developers to simulate and to share easily their designs, even if they cannot afford buying a powerful but expensive commercial piece of software. To achieve our goal we picked Icarus Verilog which is one of the most popular Verilog simulation tools. It is now being extended by a group of programmers who are concentrating their efforts on implementing support for SystemVerilog and synthesizable part of the VHDL. The final version of Icarus should allow people to simulate their mixed-language models along with testbenches written in Verilog or SystemVerilog.
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** *How to design logic synthesis and place&route tools* (Sébastien Bourdeauducq, 45 min, video CC BY-SA). While many researchers and engineers agree that several obstacles stem from the proprietary tools of the FPGA vendors, writing an alternative from scratch has always been perceived to be far too complex of a task. This perception comes largely from the lack of generic knowledge about the internals of a synthesis and place-and-route tool and the absence of published details regarding particular FPGA architectures and bitstream formats. In order to encourage the development of alternative tools, we will attempt to shed some light on these concepts and give hints about how the Xilinx Spartan-6 architecture and bitstream format work and how they could be fully understood.
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** *gEDA* (Larry Doolittle, 20 min, video CC BY-SA). gEDA is an umbrella term for a collection of Free Software EDA tools that share the philosophy of modular, flexible software that has proven so powerful in the Unix software world.  Conventional modules like schematic capture and PCB layout interact with each other, and with other gEDA tools such as simulators and footprint generators, and also with proprietary tools through documented human-readable file formats and easy scripting.  gEDA is also home to gerbv (Gerber viewer), icarus (Verilog compiler and simulator), and gtkwave (waveform viewer). While flexibility of these tools is their strength, this talk will provide
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a concrete example of how they can tie together for a single design. It will also demonstrate the user interface of the graphical tools, which has been slowly refined since 1998 (gschem) and 1994 (PCB).
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** *Kicad* (Dick Hollenbeck, 30 min, video CC BY-SA). KiCad is a an open source software tool suite for the design of printed circuit boards. It includes internationalized tools for hierarchical schematics, board layout, component assignments, gerber generation and viewing, and a calculator for board signal integrity. A quick and simple overview is given of the schematic and layout tools using sample datafiles from a working 6 layer ARM9 board. Discussed are source code quality, rate of advancement, datafile formats, project philosophies and major contributors, as these are predictors of KiCad's viability as a foundation on which to embody open source hardware designs for the OHW community.
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** *[[foss-pcb|What's missing in current FOSS PCB design tools]]* (Tomasz Wlostowski).
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** *Discussion*.
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* Coffee (15:30-16:00)
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* Session 4: Ongoing projects in labs and institutes. A selection of current projects illustrating OH practice. Here we could also discuss common platforms, both in HW and HDL.
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** *CERN OH developments* (Erik van der Bij).
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** *OH developments in Soleil* (Pascale Betinelli, 20 min, video CC BY-SA). The Synchrotron SOLEIL is a third-generation light source located near Paris. The facility receives each year more than 2500 international scientific users. SOLEIL covers fundamental research needs in physics, chemistry, material sciences, life sciences, earth sciences… In applied research, SOLEIL is involved in very different fields such as pharmacy, medicine, chemistry, petrochemistry, environment, nuclear energy, as well as nanotechnologies, micromechanics and microelectronics, and more. Many other synchrotrons are present all around the world with similar or complementary performance. Today the synchrotron community encourages collaboration and sharing of development between synchrotron facility and at the same time competition. Other synchrotron facilities are interested in some of our hardware developments and because we can share this development with them, it is evident for us (the technical team) to join the open hardware initiative. But some conditions have to be taken into account, requiring stages in the process. After a short presentation of Soleil, I will explain our mission, our organization, what we want to share and our difficulties to convince people of the interest of this initiative.
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** *The Rhino Project* (Brandon Hamilton, 20 min, video CC BY-SA). The RHINO Project is an Open Source effort born out of the radar remote sensing group at the University of Cape Town in South Africa and motivated by CASPER and the SKA Africa project. Rhino, which stands for Reconfigurable Hardware Interface for computiNg and radiO, consists of a hardware platform that includes an ARM running Borph Linux, a Spartan 6 FPGA, DDR3 memory, dual FMC-LPC as well as numerous standard IO interfaces. The goal of the project is to provide a hardware platform and software tool-chain for Software Defined Radio (SDR) which is both easy to use, easy to learn and affordable to a broad audience. It is hoped that this effort will consolidate and enhance the teaching and research resources available for Software Defined Radio (SDR), nationally and among the hacker community. This talk will provide an overview of the hardware and software that make up the Rhino ecosystem, along with some current and future applications that show the potential of the platform.
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** *Discussion*.
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h2. Participants so far
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01. Michael Abbott (Diamond Light Source Ltd).
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02. Yves-Marie Abiven (Soleil).
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03. Pablo Álvarez (CERN).
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04. Myriam Ayass (CERN).
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05. Ralph Baer (GSI).
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06. Dietrich Beck (GSI).
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07. Pascale Betinelli (Soleil).
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08. Jerôme Bisou (Soleil).
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09. Andrea Borga (NIKHEF).
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10. Sébastien Bourdeauducq (Milkymist).
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11. Charlie Briegel (Fermi National Accelerator Laboratory).
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12. Nicola Cardines (CERN).
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13. Matthieu Cattin (CERN).
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14. Jean-Pierre Charras (Kicad).
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15. Dominique Corruble (Soleil).
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16. David Cuartielles (Arduino).
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17. Don Dale (TRIUMF).
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18. Daniel de Oliveira Tavares (Brazilian Synchrotron Light Laboratory, LNLS).
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19. Nicolas di Risio (University of Pavia)
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20. Larry Doolittle (LBNL).
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21. George Fatkin (Russian Academy of Sciences).
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22. Pablo Fernández (CERN).
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23. Sébastien Franz (CERN).
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24. Kazuro Furukawa (KEK).
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25. Yukito Furukawa (Japan Synchrotron Radiation Research Institute).
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26. Philippe Gayet (CERN).
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27. Patrick Gessler (European XFEL GmbH).
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28. Guanghua Gong (Tsinghua University).
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29. Juan David González Cobas (CERN).
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30. Vincent Grennerat (UJF Grenoble).
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31. Matias Guijarro (ESRF).
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32. Steve Gunn (University of Southampton).
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33. Brandon Hamilton (University of Cape Town).
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34. Javier Herrero (HV Sistemas).
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35. Pascal Hirsch.
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36. Dick Hollenbeck (Kicad).
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37. Rok Hrovatin (Instrumentation Technologies).
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38. Billy Huang (Culham Centre for Fusion Energy).
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39. Jerzy Jamroz (CELLS-ALBA).
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40. Benjamin Jean (Inno ^3^).
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41. Mike Jennison (EURATOM/CCFE).
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42. Tomasz Jezynski (DESY).
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43. Anders Johansson (Lund University)
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44. Grzegorz Kasprowicz (Creotech).
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45. John Kenevey (Facebook).
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46. Jean-Marc Koch (ESRF).
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47. Ivan Kohler (iThemba LABS).
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48. Martin Kraimer (ANL).
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49. Mathias Kreider (GSI).
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50. Žiga Kroflic (COBIK/Cosylab).
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51. Julio Lidón (CELLS-ALBA).
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52. Maciej Lipinski (CERN).
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53. Johan Löfgren (Lund University)
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54. Ravi Marawar (National Instruments).
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55. Takemasa Masuda (Japan Synchrotron Radiation Research Institute).
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56. Óscar Matilla (CELLS-ALBA).
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57. Peter Milne (D-TACQ Solutions).
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58. Andrew Moore (University of Cambridge).
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59. Alexey Panov (Russian Academy of Sciences).
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60. Stefan Rauch (GSI)
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61. Guillaume Renaud (Soleil).
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62. Borut Repič (Instrumentation Technologies).
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63. Jean-Paul Ricaud (Soleil).
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64. Eduardo Ros (University of Granada and Seven Solutions).
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65. Alessandro Rubini (University of Pavia).
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66. Lucas Sanfelici (Sirius Project, LNLS).
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67. Stefan Schlenker (CERN)
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68. Luka Šepetavc (COBIK/Cosylab).
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69. Carlos Serrano (LBNL).
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70. Javier Serrano (CERN).
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71. Bart Sijbrandij (INCAA Computers).
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72. Pawel Szostek (Technical University Warsaw).
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73. Charilaos Tsarouchas (CERN).
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74. Isa Uzun (Diamond Light Source Ltd).
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75. Federico Vaga (University of Pavia)
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76. Erik van der Bij (CERN).
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77. Fabio Varesano (University of Torino).
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78. Axel Voitier (CERN).
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79. Tomasz Wlostowski (CERN).
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h2. Reference material
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* Third part of the document#74.
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* "Slides and notes":http://dl.dropbox.com/u/13409775/jsp_fscons2010_notes.pdf for an OH talk in FSCONS 2010 (video "part 1":http://vimeo.com/21909000 and "part 2":http://vimeo.com/21909058).