FMC Projects » RHINO

We now have 8 Rhino boards in the ether and a manufacturer in the US willing to provide you with you very own platform for a few $$$. We thought it would be a good time to more actively update the community on progress and the efforts of the various pioneers through social media. All welcome to follow and comment.
- the rhino team

It has been a while since I last added a news item. The Rhino project has still been moving along at a steady albeit slow (part time) effort. The first version of Rhino had a few minor bugs which we fixed in version 1.1. We managed to find some money to build a few more boards; 6 to be exact; with 5 working and one needing a bit of rework. Lots of effort has been spent on the software tools, which currently reside on github (linked off www.borph.org). Rhino V1.1 sports a cutting edge Borph enabled Linux 3.1 RC 1 kernel, thanks to some late night efforts from Brandon. Next step is lots of gateware.

We have finally finish setting to work the full Rhino board with a port of Borph Linux. BORPH is an operating system designed for FPGA-based reconfigurable computers, implemented as an extension of the Linux kernel. Reconfigurable hardware, such as FPGAs, are treated as computational resources within the operating system (www.borph.org)

Simon and Bruce have been busy setting to work the Rhino platform and making excellent progress. Last night we had the first successful communications between the two CX4 ports at full throttle. After 10 million 64-bit frames (simultaneous data transmission between CX4 ports), we had zero errors with a 0.5m cable. The eye diagrams look good out to 2m cables, so for long cables we will need to go optical.

The SPI interface is now working through uboot and has been used to probe the RTC and configure the FPGA.

Just three more interfaces to test! GPMC, 1Ge and FMC.

It was tight, but we made it; our first 4 prototypes have arrived and Simon is busy setting them to work. Thanks to everyone that helped! Current testing focus is on the processor subsystem. We currently have a u-boot prompt; booting from the SD Card. Progress is good and we looking forward to completing all our testing in January.

Happy New Year to All!

It has been a challenge, but we finally managed to complete the Rhino layout; thanks to a great effort by the team. The board ended up with 14 layers, a few more than we originally anticipated, but that is to be expected when most of the routes were targeted impedance, length matched and differential. All the latest Altium design files have been uploaded
to the Rhino svn repository (http://svn.ohwr.org/rhino-hardware-01). If you have the time please review and send to us feedback by the end of Monday, November 15th.

Layout has taken a bit longer than anticipated, however the end is now in sight! Supporting dual FMC-LPC connectors, DDR3 memory and various other high speed signals, placed some stringent impedance and length matching rules on many of the nets from the FPGA. As a result, the layout process was somewhat challenging. We ended up with 14 layers to accomodate all the constrained signal-ended and differential nets. For those interested we have placed an image of the Altium 3D CAD model for Rhino on the project wiki page.

• Added information to the wiki page
• Uploaded the Rhino block diagram and schematics