HDL Core Lib - Overview - Open Hardware Repository

Overview

Project to share generic HDL cores.

Subprojects: DDR3 controller for Spartan6, EtherBone Core, Gennum GN4124 core, VME64x core, Wishbone slave generator

Issue tracking

Bug: 0 open / 0
Feature: 0 open / 0
Support: 0 open / 0

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Members

Manager: Matthieu Cattin
Developer: Tomasz Wlostowski

Latest news

Wishbone b4 draft released
This new version includes a pipelined mode to cater for devices with high throughput and high latency such as DDR RAM chips.
Added by Javier Serrano 2 months ago

Wishbone slave core generator
LUA script to generate VHDL Wishbone slave interface.
Added by Matthieu Cattin 6 months ago