Overview
Project to share generic HDL cores.
- Subprojects: DDR3 controller for Spartan6, EtherBone Core, FPGA Configuration Space, Gennum GN4124 core, IPBus, LM32 processor, Platform-independent core collection, QDR II controller for Virtex 6, TDC core, VME64x core, White Rabbit core collection, White Rabbit node core, Wishbone crossbar, Wishbone Serializer Core, Wishbone slave generator
Latest news
Wishbone b4 draft released
This new version includes a pipelined mode to cater for devices with high throughput and high latency such as DDR RAM chips.
Wishbone slave core generator
LUA script to generate VHDL Wishbone slave interface.
Issue tracking
Members
Manager: Javier Serrano, Matthieu Cattin, Tomasz Wlostowski
Developer: Cesar Prados, Pablo Alvarez