Review25042012


-------------------------------------------------------------------------------
SVEC schematics review 25.04.2012
-------------------------------------------------------------------------------

MEETING SUMMARY

  + DATE           25.04.2012  15:30 - 16:30 
  + PLACE          CERN Prevessin, Building 864, Room 1-A15
  + SUBJECT        SVEC Review
  + SVN            http://svn.ohwr.org/svec/trunk/circuit_board/SVEC  
  + REVISION       13
  + PARTICIPANTS: 
      Van der Bij, Erik          EVB    Erik.van.der.Bij@cern.ch 
      Cattin, Matthieu           MC     matthieu.cattin@cern.ch    
      Wlostowski, Tomasz         TW     tomasz.wlostowski@cern.ch         
      Gil Soriano, Carlos        CGS    carlos.gil.soriano@cern.ch  
  + SUMMARY
    There are still some errors from previous review:
      -+ SCHEMATICS
        Check out the USB interface and tidy up all the project.
      -+ LAYOUT
        Special attention should be taken to the SATA connector cutouts.
        Tidy up needed.
===============================================================================
                    |         ! : fatal                 |  
                    |         + : important             |  
                    |         - : minor                 |   
                    |         ? : question              |  
                    |         * : note                  |  
                    |         A : already               |  
===============================================================================

===============================================================================
SCHEMATICS

+ SVEC_TOP.SchDoc
--+ AFPGA.SchDoc
--+ AFPGA_power.SchDoc
--+ DDR3.SchDoc
--+ DDR3_2.SchDoc
--+ FPGA_GTP.SchDoc
--+ JTAG Chain + SFPGA Flash.SchDoc
--+ SFPGA.SchDoc
--+ SFPGA_power.SchDoc
--+ USB Interface.SchDoc
--+ FMC_connectors.SchDoc
--+ VME_Connectors.SchDoc
--+ Front_panel.SchDoc
--+ Power_supplies.SchDoc
--+ Clk_generation.SchDoc

--> BOM
===============================================================================

--------------------------------------
General:
--------------------------------------
[EVB]  A- Frames should be recheck, still bad namings
[MC]   A- Use consitant naming convention for file names.
[MC]   A- Different sheets size.
[MC]   *  Re-annotation should be avoided during the review process.
          It makes hard to track changes from preview review comment,
          often based on component designator!
[MC]   -  Add a red dashed square around unmounted components (c.f. USB_connector.SchDoc).
[MC]   A- Bad naming in the sheets
[MC]   +  Add dashed lines around components that are not mounted.
[CGS]  *  PowerSupplies.Txt is not yet uploaded to repo.
[CGS]  -  VME_RETRY should be labeled as VME_RETRY_N
[CGS]  -  VME_BERR should be labeled as VME_BERR_N
[CGS]  +  The updated schematic PDF is missing. Generate and upload.

--------------------------------------

--------------------------------------
SVEC_TOP.SchDoc
--------------------------------------
[MC]   +  Bad lines for division, bad letters,...
[MC]   -  Red text describing the blocks is sometimes to small (e.g. "SFP gigabit port").
[MC]   -  I'd put AFPGA and SFPGA with a big (bold) font to clearly identify them.
[MC]   -  Unify line style to split the blocks (pink line, double blue lines).
          I'd put a single blue line everywhere.
--------------------------------------

--------------------------------------
AFPGA.SchDoc
--------------------------------------
[MC]   +  LA_18 (FMC1) should be connected to the other half-bank (LA_17 to LA_33).
[TW]   A+ R212 R240 what for?
--------------------------------------

--------------------------------------
Clk_generation.SchDoc
--------------------------------------
[MC]  ?  What is the comment box under IC12 (CDCM61004RHBT) for?
         Should be removed
[MC]  +  Display OSC3 part number.
[TW]  A+ 100 ohm resistors what for?
--------------------------------------

--------------------------------------
DDR3.SchDoc
--------------------------------------
[MC]  -  Duplicated DDR_A, DDR_DQ and DDR_BA buses.
         Remove the one under IC19H (Bank4).
--------------------------------------

--------------------------------------
DDR3_2.SchDoc
--------------------------------------
[MC]  -  Duplicated DDR_A, DDR_DQ and DDR_BA buses.
         Remove the one under IC19H (Bank4).
--------------------------------------

--------------------------------------
FPGA_GTP.SchDoc
--------------------------------------
[MC]  -  Change "SATA connectors" to "eSATA connectors".
[MC]  -  Use the same color for the text like "SATA connector", "Staight"... (c.f. FMC_connector.SchDoc).
[CGS] ? Maybe we can add directives to traces with the same length (AF12, AF14)in IC19L
--------------------------------------

--------------------------------------
JTAG Chain + SFPGA Flash.SchDoc
--------------------------------------
[MC]  -  The comment box "SFPGA configuration mode ..." is touching the ports.
         Move it a bit to the right.
[MC]  +  Change serial termination resistors to smaller values, to match the traces impedance.
--------------------------------------

--------------------------------------
SFPGA.SchDoc
----------------------------------
[MC]  -  License frame is shifted compared to the text.
--------------------------------------

--------------------------------------
USB Interface.SchDoc
--------------------------------------
[MC]  !  IC17 power supplies are badly connected.
         VIO must be connected to P3V3.
         GND and EP must be connected to GND.
[CGS] !  IC17, pins 2, 14, 15: GND is floating!
[CGS] !  IC17, pin 29 must be grounded.
[CGS] !  IC17, pin 5: VIO should be set to something.
--------------------------------------

--------------------------------------
FMC_connectors.SchDoc
--------------------------------------
[TW]  A+ FMC1_PGC2M lines (pin D1) - it's an input to the FMC. What's 4K7 series for?
--------------------------------------

--------------------------------------
VME_Connectors.SchDoc
--------------------------------------
[EVB] !  Remove JTAG lines. Are they used?
[MC]  -  License text box is outside of the sheet frame.
[MC] A+  *_DIR pullups
[MC]  +  VME_IACKIN_N connection through R209. What for?
--------------------------------------

--------------------------------------
Front_panel.SchDoc
--------------------------------------
[MC]  -  Wires color of the ESD discharge circuit is different.
--------------------------------------

--------------------------------------
Power_supplies.SchDoc
--------------------------------------
[MC]  + Use only one name per power rail.
        Change P12V_FMC1 and P12V_FMC2 to P12V_FMC.
        Change P2V5_FMC1 and P2V5_FMC2 to P2V5_FMC.
[MC]  - In comment box "DC/DC calulation...", an 'A' is missing after some ILpeak value.
[MC]  - In comment box "Power estimation...", it's writen "HPC -4A, LPC -2A".
        The '-' sign should be removed or replaced by '=' to avoid confusion.
[MC]  - PowerSupplies.Txt is missing in the repo.
[CGS] * IC18. I have checked out its values and it is OK.
--------------------------------------

--------------------------------------
BOM
--------------------------------------
[CGS] ? Can we get rid of 7K5 resistors? Only five in BOM
[CGS] ? Same for R183 and R169. 12V has a lot of margin in the compensation.
[CGS] ? R232 is the only 12K resistor. Can it be replaced and removed from BOM?
--------------------------------------

===============================================================================
LAYOUT
===============================================================================
[MC]  + A few DDR traces on the bottom are still crossing the plane on L9.
[MC]  + Copper islands between traces.
        Remove polygon fill on signal layers.
[MC]  ! P5V_VME polygon is almost cut by the power_SATA connector cutout on L4.
[MC]  ! The power_SATA connector cutout will be useless as it is.
        It should go until the edge of the board. => not possible with the VME ESD circuit!!!
[MC]  - P1V5 polygon doesn't have to go that far down on L9.
[MC]  + P12V_FMC is almost cut by H4 and H7 on Bottom layer.
[MC]  - There is a few overlapping designators (e.g. C176 and R320), and designator on vias.
[MC]  + Add test points (unmounted) for every power rail.
[MC]  ! polygon connect is too small for components on power rails!
[MC]  - Use the same font and size for all silkscreen text. 'Sherif sans' is prefered.
[MC]  + DDR_DQ15 trace has an antenna on Top layer.
[MC]  ! P12V_FMC is connected to slot 2 with only one via!
[MC]  + There is only one P12V_FMC decoupling capacitor for slot 2 (three for slot 1).
[MC]  * We should place one via per pin to connect the FMC connector power supplies.
[MC]  - Board reference should be moved to a corner.
[MC]  ? What is the text "PO VME" on the bottom? It should be removed.
[MC]   ! Remove fills in signal layers
[MC]   ! SATA connector cutout should be solved. Not possible to cut up there.
[TW]   + FMC1_LA_N0 not enough spacing with adjacent lines.
[CGS]  * Board Thickness is 59.055 mils. VME standard 1.6 mm. OK
[CGS]  - TOP:       P2V5 island could be parallel to P2V5_FMC1
[CGS]  ! L4 PWR3.3: Why P5V_VME is splitted into the big one and a small island close to STA connector?
[CGS]  ? L9 PWR:    Same for P3V3
[CGS]  * PLL_2SFPGA_PN is long. Is it critical?
[CGS]  * L3:   Islands in the way of SATA to FPGA
[CGS]  * L3:   Islands in the way of FMC1 to FPGA
[CGS]  * HSLs seem well equalized