TDC core - Overview - Open Hardware Repository

Overview

A Time to Digital Converter core for Spartan 6 FPGAs.

Status: Beta

Latest news

First test results
Added by Sebastien Bourdeauducq on 09 Nov 2011 at 22:58

Preliminary design of the data path done

40ns total latency at 125MHz with 400 taps in XC6SLX45T

Added by Sebastien Bourdeauducq on 09 Aug 2011 at 19:18

Issue tracking

Bug: 0 open / 0
Feature: 0 open / 0
Support: 0 open / 0

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Members

Manager: Guillaume Renaud, Javier Serrano, Sebastien Bourdeauducq, Tomasz Wlostowski

Companies

Milky Mist