Overview

A Time to Digital Converter core for Spartan 6 FPGAs.

  • Status: Beta

Latest news

First test results
Added by Sebastien Bourdeauducq 7 months ago

Preliminary design of the data path done
40ns total latency at 125MHz with 400 taps in XC6SLX45T
Added by Sebastien Bourdeauducq 10 months ago

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Members

Manager: Javier Serrano, Sebastien Bourdeauducq, Tomasz Wlostowski

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