Project description

The TDC core is a high precision (sub-nanosecond) time to digital conversion core for Xilinx Spartan-6 FPGAs.

Specifications

  • Measured precision: +/- 52ps (95% confidence).
  • Fixed point output:
    • Integer part is number of FPGA clocks (coarse counter).
    • 13-bit fractional part.
    • With a 125MHz FPGA clock, LSB corresponds to 0.98ps.
  • Typical range: 268ms (using a <25.13>-bit value at 125MHz).
    • Number of coarse counter bits configurable with a VHDL generic.
  • Latency: 6 cycles at 125MHz (not including host interface module).
  • Multiple channels.
    • Configurable with a VHDL generic.
    • Calibration logic shared between channels.
  • Reports both rising and falling edges of the input signal.
  • Input signal must not have transitions shorter than three times the FPGA clock period.
  • Uses a counter for coarse timing and a calibrated delay line for fine timing.
  • Delay line implemented with carry chain (CARRY4) primitives.
  • Calibration mechanism:
    • at startup (and after receiving a reset command), send random pulses into the delay line (coming from e.g. a on-chip ring oscillator), build histogram, compute delays (as explained in the Fermilab paper), initialize the LUT, and measure the frequency of the compensation ring oscillator.
    • for online temperature/voltage compensation, measure again the frequency of the ring oscillator, compare it to the frequency measured at start-up, linearly interpolate the delays, and update the LUT.
  • "Wave union" not implemented.
  • Input signals (without host interface module):
    • Input signal.
    • Calibration signal.
    • Coarse counter reset.
    • Per-channel de-skew value.
    • Full reset (and recalibrate).
    • Clock.
  • Output signals (without host interface module):
    • Startup calibration in progress.
    • Periodic counter overflow.
    • Received rising/falling edge notification:
      • Strobe signal.
      • Rising/falling edge.
      • Fixed point timestamp.
      • Raw encoded value from the delay line.
  • Debug interface:
    • Forced switch to the calibration signal.
    • Access to the histogram values from the startup calibration.
    • Access to the frequencies of the online calibration ring oscillators.
  • Optional host/CPU interface module:
    • Wishbone slave.
    • Configuration and status registers.
    • Interrupts: edge received, counter overflow.

Deliverables

Status

Date Event
18/07/2011 Project started.
28/07/2011 Specification written.
01/08/2011 Development started.
05/08/2011 Basic data path of the TDC (delay line + encoder + LUT) designed. Timing is met at 125MHz with a 400-tap ~12ns delay line. Total latency is 5 cycles (40ns).
21/08/2011 "Alpha" design done. Still needs more test benches and documentation.
26/08/2011 Host interface module done.
28/08/2011 "Beta" design done. PDF documentation is in the "Documents" section.
21/10/2011 Hardware tests started.
09/11/2011 Test results available.

Envisioned applications

Other works

  • Claudio Favi and Edoardo Charbon: A 17ps Time-to-Digital Converter Implemented in 65nm FPGA Technology PDF
  • Jinyuan Wu and Zonghan Shi: The 10-ps Wave Union TDC: Improving FPGA TDC Resolution beyond Its Cell Delay PDF