Overview

A VHDL core for a VME64x slave (Wishbone master).

  • Status: Alpha

Issue tracking

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Members

Manager: Joze Dedic, Pablo Alvarez, Rok Stefanic
Developer: Andrea Boccardi, Carlos Gil Soriano, Matthieu Cattin, Tomasz Wlostowski, Ziga Kroflic
Reporter: Andrea Boccardi, Carlos Gil Soriano, Matthieu Cattin, Tomasz Wlostowski

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