wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:
- Automatically allocated memory layout
- VHDL/Verilog code for the slave module
- C header files for driver development
- Nice HTML documentation

Read the wbgen2 Documentation
Get the latest version: <a class="external" href="http://www.ohwr.org/attachments/download/112/wishbone-gen-r1.tar.gz">http://www.ohwr.org/attachments/download/112/wishbone-gen-r1.tar.gz</a>

  • Status: Release